Semiconductor chip and method of forming same

Abstract

A method for forming a semiconductor chip is provided, comprising: providing a silicon carrier wafer, which has a first surface and a second surface, wherein an epitaxial III-V group semiconductor region and an oxidized region are arranged on the first surface, and an epitaxial III-V group The semiconductor region and the oxide region have approximately the same height measured from the first side of the silicon carrier wafer, and the sidewalls of the epitaxial III-V group semiconductor region contact the sidewalls of the oxide region; formed on the top surface of the epitaxial III-V group semiconductor region and the oxide region Eutectic bonding layer; bonding CMOS wafer to eutectic bonding layer; subsequent removal of silicon carrier wafer; singulating CMOS wafer to form three-dimensional integrated circuits, both comprising CMOS substrate and III The ‑V optical device, the CMOS substrate and the III‑V optical device correspond to a part of the CMOS chip and the III‑V optical device, respectively.

Description

technical field [0001] Embodiments of the present invention relate to a semiconductor chip and a method for forming the same, and more particularly to a semiconductor chip for wafer-to-wafer bonding and a method for forming the same. Background technique [0002] It is well known that semiconductor chips are used in all kinds of electronic components and other devices. Today's widespread use of such chips, coupled with consumer demand for more powerful and smaller devices, has led chip manufacturers to continually reduce the physical size of chips and increase their functionality. To shrink chip footprints, manufacturers are increasingly pushing to achieve smaller feature sizes and die sizes, allowing more dies to fit within a given size wafer. To shrink the height of chips, manufacturers have worked hard to create three-dimensional or stacked integrated circuits (3DIC's). Existing methods of manufacturing these stacked chips, such as the pick-and-place method used to bond...

AI Technical Summary

Problems solved by technology

Existing methods of manufacturing these stacked chips, such as the pick-and-place method used to bond individual chips to other chips or wafers, can be time consuming

The higher the density of die in a given wafer size, the longer this bonding process takes, which reduces manufacturing throughput measured in wafers bonded per hour

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