Method of manufacturing a semiconductor device and a semiconductor device

Abstract

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers, the second semiconductor layer and an upper portion of the fin structure at a source / drain region of the fin structure, which is not covered by the sacrificial gate structure, are etched. A dielectric layer is formed over the etched upper portion of the fin structure. A source / drain epitaxial layer is formed. The source / drain epitaxial layer is connected to ends of the second semiconductor wires, and a bottom of the source / drain epitaxial layer is separated from the fin structure by the dielectric layer.

Description

technical field [0001] The present invention relates to methods of fabricating semiconductor integrated circuits, and more particularly, to methods and semiconductor devices of fabricating semiconductor devices including Fin Field Effect Transistors (FinFETs) and / or Gate All Around (GAA) FETs. Background technique [0002] As the semiconductor industry enters nanotechnology process nodes in pursuit of higher device density, higher performance, and lower cost, challenges from manufacturing and design issues have given rise to applications such as multi-gate field-effect transistor (FET) (including fin FETs (FinFETs) and gate-all-around (GAA) FETs). In a FinFET, the gate electrode is adjacent to three sides of the channel region with a gate dielectric layer interposed between them. Because the gate structure surrounds (wraps) the fin from three surfaces, the transistor basically has three gates that control the current flow through the fin or channel region. Unfortunately, t...

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Problems solved by technology

Unfortunately, the fourth side, the bottom of the channel is far from the gate electrode and thus not under close gate control

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