Semiconductor power device and preparation method thereof

Abstract

The invention provides a semiconductor power device and a preparation method thereof. The semiconductor power device comprises a substrate, a lightly doped well region, a heavily doped well region, asource region, a gate oxide layer, a gate electrode, a first insulating dielectric layer, a thermal oxide layer, a second insulating dielectric layer and a front-surface metal, wherein the second insulating dielectric layer is disposed above the thermal oxide layer and covers an upper surface of the thermal oxide layer. Therefore, the width of the source region is small, thereby reducing a parasitic resistance under the source region and improving the anti-latching ability; the stability of performance parameters is high and the product yield is high.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a semiconductor power device and a preparation method thereof. Background technique [0002] Semiconductor power devices are semiconductor devices capable of handling high voltage and high current. With the rapid development of new power semiconductor devices represented by power MOSFET devices, semiconductor power devices are now widely used. New power semiconductor devices represented by power MOSFETs include VDMOS, LDMOS, and IGBT, etc. VDMOS (vertical double-diffusion MOSFET) is a vertical device, mostly used in discrete devices; LDMOS (Lateral double-diffusion MOSFET) is a horizontal device, its three electrodes are all on the surface of the silicon chip, easy to integrate, and mostly used in the field of power integrated circuits; IGBT (Insulated Gate Bipolar Transistor Insulated Gate Bipolar Transistor), can be regarded as a hybrid new device of power MOS and power BJT. How...

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Problems solved by technology

[0006] The contact hole process of the IGBT emitter and the VDMOS source usually uses photolithographic selective etching. The inventors found that the distance from the contact hole electrode to the gate polysilicon will be different due to problems such as alignment deviation and line width deviation of the contact hole photolithography. Fluctuations, resulting in fluctuations in the N+ width of the device, causing fluctuations and deviations in device parameters (such as anti-latch capability), especially when the design margin is low, device parameters fluctuate greatly, and even cause device failure

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