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A circuit structure for relieving circuit aging and its control method

A technology of circuit structure and control method, applied in the direction of logic circuit, logic circuit with logic function, electrical components, etc., can solve the problem of disturbing the optimal input vector to circuit control, input vector control method is difficult to play, large-scale circuit optimization The effect is not obvious and other problems, to achieve the effect of improving the optimization effect

Active Publication Date: 2022-07-26
ANHUI UNIV OF SCI & TECH
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Problems solved by technology

[0006] The technical problem to be solved by the present invention is that the gate replacement circuit and control method for alleviating circuit aging in the prior art disrupt the control of the circuit by the optimal input vector, and the input vector control method is difficult to play its role, and the optimization of large-scale circuits Problems with little effect

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  • A circuit structure for relieving circuit aging and its control method
  • A circuit structure for relieving circuit aging and its control method
  • A circuit structure for relieving circuit aging and its control method

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Embodiment Construction

[0021] The embodiments of the present invention are described in detail below. This embodiment is implemented on the premise of the technical solution of the present invention, and provides a detailed implementation manner and a specific operation process, but the protection scope of the present invention is not limited to the following implementation. example.

[0022] like figure 2 As shown, a circuit structure for alleviating circuit aging includes a NOR gate G4 and NAND gates G7, G8, G9, G5 and G6, the output terminals of the NAND gate G7 are respectively the second input of the NOR gate G4 terminal and the first input terminal of the NAND gate G9, the output terminal of the NAND gate G8 is respectively connected with the second input terminal of the NAND gate G9 and the second input terminal of the NAND gate G6, the NAND gate The output terminal of G9 is respectively connected with the second input terminal of the NAND gate G5 and the first input terminal of the NAND ga...

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Abstract

The invention discloses a circuit structure for alleviating circuit aging and a control method thereof, including a NOR gate G4 and NAND gates G7, G8, G9, G5 and G6, and the output ends of the NAND gate G7 are respectively NAND gate G4. The second input terminal is connected to the first input terminal of the NAND gate G9, the output terminal of the NAND gate G8 is connected to the second input terminal of the NAND gate G9 and the second input terminal of the NAND gate G6 respectively, and the NAND gate G9 The output terminals of the NAND gate G5 are respectively connected with the second input terminal of the NAND gate G5 and the first input terminal of the NAND gate G6; a control method of the circuit structure for alleviating circuit aging is to first protect the key gate G3, and then protect the key gate G5 and G6, and finally use the input vector control method to protect the key gate that cannot be protected by the gate replacement method; the present invention can not only solve the problem of the gate replacement method destroying the optimization effect of the input vector control method on the circuit existing in the existing method for alleviating circuit aging, It can also improve the aging mitigation effect of the input vector control method on large circuits.

Description

technical field [0001] The invention relates to the field of aging mitigation of integrated circuits, and more particularly to a circuit structure and a control method thereof for alleviating circuit aging. Background technique [0002] The NBTI effect refers to the degradation of a series of electrical parameters caused by the application of negative gate voltage to the PMOSFET at high temperature (general stress conditions are gate oxide electric field at a constant temperature of 125 °C, source, drain and substrate are grounded). [0003] As the size of the transistor fabrication process continues to shrink, the Negative Bias Temperature Instability (NBTI) effect has gradually become the main factor that causes the aging and even failure of integrated circuits. In order to alleviate the circuit aging caused by the NBTI effect, scholars at home and abroad have proposed many methods, among which the most commonly used method is the combination of the input vector control me...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/00H03K19/20
CPCH03K19/0013H03K19/20
Inventor 徐辉王威猛孙侠赵前进方贤进
Owner ANHUI UNIV OF SCI & TECH
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