A novel cache optimization multi-thread determinacy method

A cache optimization, multi-threading technology, applied in multi-program device, program synchronization, inter-program communication, etc., can solve problems such as interference, parallel program uncertainty, competition, etc.

Pending Publication Date: 2019-03-15
HARBIN INST OF TECH AT WEIHAI
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  • Abstract
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  • Application Information

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Problems solved by technology

[0003] Despite the standard library support, parallel programs bring challenges to program development and maintenance while improving computing performance compared to traditional serial programs.
Parallel programs usually have multiple parallel execution individuals cooperate to complete a ta...

Method used

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  • A novel cache optimization multi-thread determinacy method
  • A novel cache optimization multi-thread determinacy method
  • A novel cache optimization multi-thread determinacy method

Examples

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Embodiment

[0017] refer to figure 1 , set a fence for thread running in the parallel stage, each parallel stage can only allow the thread to execute a certain number of instructions, after the execution is completed, the thread is blocked by the fence, waiting for other threads to enter the synchronous operation.

[0018] In the serial stage, the thread obtains the token according to the token passing algorithm at the synchronization point, applies for locking the memory, and then submits the execution result. Obtaining tokens and applying for locks are mutually exclusive actions, and each thread can only execute it once in each round. Threads are blocked by the fence after performing the submission operation, and wait for the following threads to enter the serial phase. After all threads have completed the serial phase, the threads submit their own private pages to the shared page, compare with the shared page, and obtain The latest shared data after this round of execution prepares fo...

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Abstract

The invention provides a multi-thread deterministic method based on cache optimization. The multi-thread deterministic method comprises a thread deterministic structure module, a multi-thread communication isolation module, an atomic transaction stage division module, a thread synchronization strategy research module and LIRS cache optimization. The method can be used for guaranteeing thread deterministic execution of tasks in a multi-thread system, extra system overhead brought by a deterministic method is optimized, and synchronous competition and data competition brought by thread uncertainoperation are prevented. Thread operation stages are divided by taking transactions as units, threads are executed in parallel in the parallel stage, thread communication is isolated, and a fence isset for global synchronization. And the thread in the serial stage obtains tokens through a deterministic sequence, and executes submission to a memory in sequence to execute deterministic scheduling.Due to the fact that communication isolation between threads and caching become the last-stage shared storage, an LIRS cache replacement algorithm more suitable for multiple threads is adopted to optimize the system performance, and therefore the system overhead is reduced while the multi-thread operation certainty is guaranteed.

Description

technical field [0001] The invention is applied to ensure the determinism of thread running in a multi-thread environment. Background technique [0002] With the development of microelectronics technology, on-chip multi-core processors have become the mainstream computing platform and research hotspot. Compared with the previous single-core processors, multi-core processors have achieved explosive improvement in hardware performance. The traditional serial program can no longer play its performance. Parallel programming is the key to give full play to its multi-core performance. The only programming way for mainstream applications to benefit from the performance of multi-core CPUs. [0003] Despite the standard library support, compared with traditional serial programs, parallel programs bring challenges to program development and maintenance while improving computing performance. Parallel programs usually have multiple parallel execution individuals cooperate to complete ...

Claims

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Application Information

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IPC IPC(8): G06F9/52G06F9/54
CPCG06F9/526G06F9/544
Inventor 王开宇季振洲吴倩倩张源悍王楷
Owner HARBIN INST OF TECH AT WEIHAI
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