Parallel processing method, device and readable storage medium for solid state hard disk data
A solid-state hard disk and parallel processing technology, applied in the direction of electrical digital data processing, input/output process of data processing, instruments, etc., can solve the problems of control channel and chip selection parallel prone to defects, etc., to reduce debugging time and avoid defects , the effect of reducing the burden
Active Publication Date: 2021-11-26
YEESTOR MICROELECTRONICS CO LTD +1
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Problems solved by technology
[0003] The main purpose of the present invention is to provide a parallel processing method, device and readable storage medium for solid-state hard disk data, aiming to solve the problem in the prior art that the parallel between the control channel and the chip selection through firmware is prone to defects
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[0077] refer to image 3 , the first embodiment of the parallel processing method of solid-state hard disk data of the present invention, the parallel processing method of solid-state hard disk data comprises the following steps:
[0078] Step S10, after the current chip select of the target channel has performed the corresponding operation, using the current chip select as a starting point, cyclically detect whether there is a chip select in the target channel in an idle state according to a preset sequence;
[0079] In this embodiment, the multiple channels do not interfere with each other and are used to perform operations on the flash memory array in parallel. Only the corresponding operation under a certain chip selection can be performed. After the current chip selection has performed the corresponding operation, the current chip selection will immediately enter the RB state (the busy state of the flash memory array), and the RB state will continue for a certain period o...
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The invention discloses a parallel processing method, device, and computer-readable storage medium for solid-state hard disk data. The parallel processing method for solid-state hard disk data includes the following steps: The current chip selection is used as the starting point, and the hardware is used to circularly detect whether there is a chip selection in the target channel in an idle state according to a preset order; when it is detected that a chip selection is in an idle state, then the corresponding Obtain the mapping address corresponding to the next operation in the head of the linked list; obtain the relative offset value corresponding to the next operation in the linked list buffer according to the mapping address, and obtain the next operation according to the relative offset value An operation controls the operation information of the buffer area, and controls the chip select in the idle state to execute the next operation. The invention has the technical effect of obtaining the best execution sequence of operations through the linked list data structure.
Description
technical field [0001] The invention relates to the technical field of data storage, in particular to a parallel processing method, device and readable storage medium for solid state hard disk data. Background technique [0002] In the prior art, in order to make solid-state drives (SSD) products have faster read and write speeds, the flash memory controller has multiple channels and many chip selects to control the non-volatile flash memory (Flash), and it is not easy to achieve parallel operation. The effect of volatile flash memory. In the prior art, the parallelism between the channel and the chip selection is controlled by the built-in firmware (FW, Firmware) in the flash memory controller, and a large amount of software codes are required to ensure the parallelism between the channel and the chip selection, but the software code Defects (Bugs) are prone to occur, and debugging time is required, and the execution process consumes a lot of CPU resources. Contents of t...
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IPC IPC(8): G06F3/06
CPCG06F3/061G06F3/0629G06F3/0688
Inventor 翁敏博吴大畏李晓强黄慧
Owner YEESTOR MICROELECTRONICS CO LTD