Semiconductor chip packaging method and package structure

Abstract

The invention discloses a chip packaging method and a package structure. The semiconductor packaging method comprises the steps of: providing a first carrier on which at least one predetermined position is disposed; mounting at least one semiconductor chip on the predetermined position of the first carrier; providing at least one metal structure, the metal structure comprising at least one metal unit; mounting the metal structure on the first carrier, wherein the metal unit corresponds to at least one semiconductor chip; and encapsulating the at least one semiconductor chip and the at least one metal structure. The invention achieves improvement of packaging performance due to different metal features by mounting the preformed metal structure comprising a plurality of metal units on the first carrier.

Description

[0001] This disclosure claims priority to Patent Application No. 10201707457X filed in Singapore on 12 September 2017, which is hereby incorporated by reference in its entirety. technical field [0002] The present disclosure relates to the field of semiconductor technology, in particular to a semiconductor chip packaging method and packaging structure. Background technique [0003] In the prior art, a common chip packaging technology mainly includes the following process: firstly, the front surface of the chip is bonded to the substrate wafer by adhesive tape, wafer-level plastic packaging is performed, the substrate wafer is peeled off, and then the chip is sealed on the substrate wafer. Rewiring is performed on the front side to form a rewiring layer, and solder balls are planted, and finally the package is cut into individual pieces. [0004] In the packaging process, if it is necessary to arrange a metal structure around the chip so as to be electrically connected to th...

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Problems solved by technology

[0004] During the packaging process, if a metal structure needs to be provided around the chip for electrical connection with the chip, the usual practice is to pass electroplating on the first metal carrier The manufacturing process produces the required metal conductor at the predetermined position of the first carrier plate, but the thickness of the electroplated metal layer produced by this manufacturing process is limited, which does not meet the needs of high-current products that require good thermal and electrical properties; Moreover, according to actual needs, when forming personalized metal features on the chips in the board-level package, it is necessary to use the electroplating process to set them up one by one, and the electroplating process is costly and time-consuming, so the use of this process is not conducive to the formation of local metal features.

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