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Test system for System in Package (SiP) based on JTAG interface

A test system and interface technology, applied in the field of SiP packaging test systems, can solve problems such as high cost, complex test logic, and incompatibility with the JTAG protocol.

Inactive Publication Date: 2019-04-05
58TH RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The current SiP self-test technology based on the JTAG interface is not compatible with the standard JTAG protocol, and the test logic is relatively complicated and the cost is high

Method used

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  • Test system for System in Package (SiP) based on JTAG interface
  • Test system for System in Package (SiP) based on JTAG interface
  • Test system for System in Package (SiP) based on JTAG interface

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Embodiment Construction

[0023] Preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0024] In order to achieve the purpose of the present invention, as figure 1 As shown, in one of the embodiments of the present invention, a test system for SiP packaging based on the JTAG interface is provided, including a JTAG interface, a SOC TAP controller, an instruction register, and a MUX module for TDO output. The JTAG The interface is electrically connected to the input end of the SOC TAP controller for controlling the SOC TAP controller, and the output end of the SOC TAP controller is electrically connected to the input end of the instruction register for sending the instruction of the SOC TAP controller to the instruction register, the output end of the instruction register is electrically connected to the input end of the MUX module for outputting the control signal of the corresponding test mode according to the instruction recei...

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Abstract

The invention discloses a test system for System in Package (SiP) based on a JTAG interface. The test system comprises a JTAG interface body, a SOC TAP controller, an instruction register and a MUX module for TDO output, wherein the JTAG interface body is used for controlling the SOC TAP controller, the SOC TAP controller is used for sending an instruction of the SOC TAP controller to the instruction register, the instruction register is used for outputting a corresponding test mode control signal according to the instruction received by the instruction register, and the output end of the instruction register is further electrically connected to the input end of a required test device. The test system allows a plurality of debugging tools to access and debug the TAP controllers of correspondingly debugged kernels without affecting the debugging operations on other kernels, and has the advantages of simple structure and compatibility with a JTAG protocol.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit testing, and in particular relates to a testing system for SiP packaging based on a JTAG interface. Background technique [0002] System-in-Package (SiP) is a single standard package that preferentially assembles multiple active electronic components with different functions and optional passive devices, as well as other devices such as MEMS or optical devices, to achieve certain functions. , forming a system or subsystem. In terms of architecture, SiP integrates multiple functional chips, including SoC, ADC, DAC, memory, LDO, etc. challenges, especially as the integrated chips operate at higher frequencies and more pins. As an important research hotspot, SiP testing technology has achieved many research results. As a standard designed for testing and debugging, JTAG is often embedded in large-scale integrated circuits, such as SoC, CPU, DSP, FPGA, etc., so multiple devices in SiP ma...

Claims

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Application Information

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IPC IPC(8): G01R31/28G01R1/04
CPCG01R1/0433G01R31/2896
Inventor 张磊杨亮魏敬和
Owner 58TH RES INST OF CETC