BTB fusion method under prefetching mechanism

Abstract

The invention belongs to the technical field of central processing units. The invention relates to a BTB fusion method, in particular to a BTB fusion method under a prefetching mechanism. The method comprises the following steps of: S1, executing an address calculation instruction by Dispatch, S2, returning to the front-end value taking stage to carry out pre-taking operation and storing the pre-taking operation into a pre-taking structure; S3, the Dispach executes the jump instruction; The BTB fusion method under a prefetching mechanism is reaseable in design, the performance gain brought bythe instruction scheduling of the prefetching mechanism can be exerted; the insufficient front-end instruction fetching performance caused by untimely prefetching under an extreme instruction sequencecan be made up through BTB. The method has the advantages that the risk of performance loss caused by BTB prediction errors is reduced, the advantages of a compiler and hardware collaborative optimization are brought into play, the influence of the BTB prediction errors on front-end fetch bandwidth is reduced through a fusion structure, and meanwhile instruction scheduling pressure is fully relieved.

Description

technical field [0001] The invention relates to the technical field of central processing units, in particular to a method for merging BTBs under a prefetching mechanism. Background technique [0002] The front-end instruction fetch bandwidth of a traditional CPU depends on branch direction prediction and branch address prediction, and the cache miss during the instruction fetch process or front-end bubbles caused by branch prediction jumps are covered by the instruction fetch buffer. Therefore, the prediction accuracy determines the entire front-end instruction fetch. Energy-efficiency ratio, the extreme instruction sequence will make the branch difficult to predict, whether it is the direction or the jump address prediction error will bring a lot of performance loss, and increase the pressure of instruction scheduling, for this reason, we propose a predictive Take the method of fusing BTB under the mechanism. Contents of the invention [0003] The purpose of the present...

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Problems solved by technology

[0003] The purpose of the present invention is to provide a method for merging BTB under the prefetching mechanism to solve the problem that the extreme instruction sequence proposed in the above-mentioned background technology will make the branch difficult to predict, and no matter the direction or the prediction error of the jump address will bring A large performance loss, and increase the pressure of instruction scheduling, and provide another design idea: define a class of branch address calculation instructions, and have their own architecture registers, and initiate instruction fetches every time the address calculation is performed Request, and store the cache line in advance, associate the branch instruction that needs to jump to the address with the cache line prefetched by address calculation through renaming, and apply BTB technology to make up for the lack of instruction scheduling. The address calculation instruction and the branch instruction are too close together Come to the front end bubble

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