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Anti-Multi-Bit Flip Error Chip Hardening Method Based on Improved Triple-Mode Redundant System

A technology of triple-mode redundancy and multi-bit inversion, which is applied in the direction of fault handling not based on redundancy, error detection of redundant data in hardware, generation of response errors, etc., and can solve the delay of voting results and the failure of module registers Repair and fail to timely detect module data and other problems, to achieve the effect of improving system reliability and eliminating multi-bit flip errors

Active Publication Date: 2022-04-05
INST OF ELECTRONICS ENG CHINA ACAD OF ENG PHYSICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This traditional TMR structure only judges the output of the module, and cannot detect the data inside the module in a timely manner, which will cause a delay in the voting result. In addition, this structure only selects the output of the module without errors from the voting result, and cannot correct the output of the module. Faulty modules perform register repair

Method used

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  • Anti-Multi-Bit Flip Error Chip Hardening Method Based on Improved Triple-Mode Redundant System
  • Anti-Multi-Bit Flip Error Chip Hardening Method Based on Improved Triple-Mode Redundant System
  • Anti-Multi-Bit Flip Error Chip Hardening Method Based on Improved Triple-Mode Redundant System

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Embodiment Construction

[0029] The technical solution of the present invention will be further described below in conjunction with the accompanying drawings of the description.

[0030] The improved three-mode redundant system involved in this application includes a controller, a set of main modules, two sets of redundant modules and a voter array. The controller establishes communication connections with the main module, redundant modules and voter array respectively. Judging the circuit by receiving the voting result of the voter array, the controller is used to call the correct data in the voter array when the circuit enters the restorative debugging state, and write the correct data to the register in the flipped module Middle; the voter array contains several groups of sub-voters, the number of sub-voters is the same as the number of registers in any one of the three groups of modules, and the sub-voters are used to receive the value of the registers at the same position in the three groups of mo...

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Abstract

The invention discloses a multi-bit flip error chip reinforcement method based on an improved triple-mode redundant system, and relates to the technical field of digital integrated circuits. The present invention compares the state value of the internal register of the digital integrated circuit, and then judges the register where the single event reversal occurs, and outputs the control signal through the voting device, and copies the register value of the digital integrated circuit that has not occurred the single event reversal to the register value that the single event reversal has occurred. registers to complete the function of digital integrated circuit error correction.

Description

technical field [0001] The present invention relates to the technical field of digital integrated circuits, in particular to the technical field of digital integrated circuit core error correction mechanism, and more specifically to a multi-bit flip error-resistant chip reinforcement method based on an improved triple-mode redundant system. Background technique [0002] With the rapid development of applications such as high-speed wireless communication, high-speed data acquisition and measurement in recent years, people's demand and research on SOC (System-on-Chip) is becoming more and more urgent. Almost all electronic systems integrate several blocks or even Dozens of SOCs. The manufacture of SOC chips utilizes a large amount of semiconductor materials. The radioactive impurities in these materials will release charged particles such as α particles during the decay process. pair of holes. [0003] Normally, the probability of single-event upset in an integrated circuit ...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/20G06F11/07
CPCG06F11/0793G06F11/2058
Inventor 贺迅刘友江马建平解楠周劼
Owner INST OF ELECTRONICS ENG CHINA ACAD OF ENG PHYSICS