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Integrated circuit electrostatic discharge bus structure and related method

一种集成电路、总线的技术,应用在集成电路静电放电总线结构领域,能够解决内电路版图设计缺乏灵活性、增大生产成本、集成电路ESD总线结构浪费等问题

Active Publication Date: 2019-04-26
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the portion of circuit area 10 occupied by filler cells F1 and F2 is wasteful for integrated circuit ESD bus structures
Furthermore, under the strict requirement of the integrated circuit ESD bus structure 1 having a rectangular shape, it leads to a lack of flexibility in the layout design of the inner circuit
[0005] Furthermore, when there are circuits with irregular shapes and different areas, the circuit area 10 must be enlarged to contain the circuits with irregular shapes and different areas, which increases production costs

Method used

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  • Integrated circuit electrostatic discharge bus structure and related method
  • Integrated circuit electrostatic discharge bus structure and related method
  • Integrated circuit electrostatic discharge bus structure and related method

Examples

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Embodiment Construction

[0018] figure 2 is a schematic diagram of an integrated circuit electrostatic discharge (ESD) structure 2 according to an embodiment of the present invention. The integrated circuit ESD bus structure 2 includes a circuit area 20 , a plurality of ESD buses E1 , E2 and E3 , a plurality of pad groups G1 , G2 and G3 , a common ESD bus 24 , and a plurality of bond wires 25 .

[0019] The circuit area 20 is formed by a plurality of chip edges 23 ; for example, four chip edges 23 form a rectangular area configured to contain the circuit area 20 . The circuit area 20 includes a plurality of discontinuous boundaries B1, B2 and B3. A plurality of ESD buses E1, E2, and E3 are formed inside chip edge 23, corresponding to and adjacent to a plurality of discontinuous boundaries B1, B2, and B3.

[0020] A plurality of pad groups G1, G2 and G3 are formed inside the chip edge 23 adjacent to and connected to a plurality of ESD bus lines E1, E2 and E3. The common ESD bus 24 is formed outside ...

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PUM

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Abstract

An integrated circuit ESD bus structure includes: a circuit area; a plurality of electrostatic discharge (ESD) buses; a plurality of pad groups adjacent to and connected to the plurality of ESD buses;a common ESD bus; and a plurality of bonding lines configured to connect the plurality of pad groups to the common ESD bus.

Description

technical field [0001] The present invention relates to integrated circuit structures and related methods, and more particularly, to integrated circuit electrostatic discharge bus structures and related methods. Background technique [0002] For an integrated circuit electrostatic discharge (hereinafter abbreviated as ESD) structure 1 as shown in FIG. , wherein the placement of the I / O pad 12 can be adjusted within a certain range. [0003] Typically, filler cells F1 and F2 are typically placed in the empty space between I / O pads 12 and are connected to electrostatic discharge (ESD) bus 11 (e.g., to ground or system voltage Layout traces of the circuit area 10 , which connects each portion of the circuit area 10 and the filler cells F1 and F2 to a continuous ESD bus to provide ESD protection for the integrated circuit ESD bus structure 1 . [0004] However, the portion of circuit area 10 occupied by filler cells F1 and F2 is wasteful for integrated circuit ESD bus structur...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02H01L23/49H01L21/60
CPCH01L24/48H01L24/85H01L27/0292H01L2224/48101H01L2224/4813H01L2224/48091H01L2224/852H01L2224/04042H01L2224/06135H01L24/06H01L23/49H01L23/50H01L27/0248
Inventor 李志国
Owner YANGTZE MEMORY TECH CO LTD