Integrated circuit electrostatic discharge bus structure and related method
一种集成电路、总线的技术,应用在集成电路静电放电总线结构领域,能够解决内电路版图设计缺乏灵活性、增大生产成本、集成电路ESD总线结构浪费等问题
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[0018] figure 2 is a schematic diagram of an integrated circuit electrostatic discharge (ESD) structure 2 according to an embodiment of the present invention. The integrated circuit ESD bus structure 2 includes a circuit area 20 , a plurality of ESD buses E1 , E2 and E3 , a plurality of pad groups G1 , G2 and G3 , a common ESD bus 24 , and a plurality of bond wires 25 .
[0019] The circuit area 20 is formed by a plurality of chip edges 23 ; for example, four chip edges 23 form a rectangular area configured to contain the circuit area 20 . The circuit area 20 includes a plurality of discontinuous boundaries B1, B2 and B3. A plurality of ESD buses E1, E2, and E3 are formed inside chip edge 23, corresponding to and adjacent to a plurality of discontinuous boundaries B1, B2, and B3.
[0020] A plurality of pad groups G1, G2 and G3 are formed inside the chip edge 23 adjacent to and connected to a plurality of ESD bus lines E1, E2 and E3. The common ESD bus 24 is formed outside ...
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