A function verification method and system applied to ahb bus matrix design

Abstract

The invention discloses a function verification method and system for an AHB bus matrix. The method comprises the steps that AHB bus excitation is randomly generated; according to a slave device baseaddress and an offset address which can be accessed by the master device, AHB bus excitation is taken as master equipment data according to the time sequence requirement of an AHB bus protocol and sent to an AHB bus matrix, a slave equipment result is output through the AHB bus matrix, and behaviors and states of all slave equipment are simulated according to the slave equipment result and serve as return data to be returned to the AHB bus matrix; and the returned data passing is compared through the AHB bus matrix with the slave device result and the AHB bus excitation meeting the time sequence requirement of the AHB bus protocol. Functional verification of the AHB bus matrix can be completed without depending on AHB IP core verification, efficiency is higher, and functional verificationof the AHB bus matrix is easier to achieve.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a function verification method and system applied to AHB bus matrix design. Background technique [0002] With the increasing scale of integrated circuit chips, digital chip design has developed from a timing-driven design method to a design method based on IP core multiplexing, and has been widely used in SoC design. Among them, the AHB bus matrix inside the SoC is usually the core and key of the entire circuit design. It can enable multiple master devices to access different slave devices in parallel and manage the data transmission of the chip. The AHB bus matrix inside the SoC is built by the IP core. Before the functional verification of the SOC bus matrix, the traditional method must first verify the IP core. This verification method relying on the AHB IP core has many processes and low efficiency. Moreover, the current chip success rate is low at one time, ma...

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Problems solved by technology

[0003] The purpose of the present invention is to provide a functional verification method and system applied to the design of AHB bus matrix, which is used to solve the problems of low success rate of one-time casting of existing chips and insufficient verification

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