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Memory system and control method

A memory system and memory technology, applied in memory systems, instruments, memory architecture access/allocation, etc., can solve the problems of complex control of NAND-type flash memory

Active Publication Date: 2021-12-31
株式会社PANGEA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] However, in general, since the control of NAND type flash memory is relatively complicated, when implementing a new interface for improving I / O (Input / Output, input / output) performance, it is necessary to consider the host computer and memory (memory system). ) Appropriate sharing of roles between

Method used

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  • Memory system and control method

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Embodiment Construction

[0048] Embodiments will be described below with reference to the drawings.

[0049] First, refer to figure 1 , the configuration of a computer system including a memory system according to an embodiment will be described.

[0050] This memory system is a semiconductor memory device configured to write data into a nonvolatile memory and read data from the nonvolatile memory. This memory system is implemented as a flash memory device 3 based on NAND flash technology.

[0051] The computer system may also include a host (host device) 2 and a plurality of flash memory devices 3 . The host computer 2 may also be a server configured to use a flash memory array composed of a plurality of flash memory devices 3 as a memory. The host (server) 2 and the plurality of flash storage devices 3 are connected to each other (interconnected internally) via the interface 50 . The interface 50 for internal interconnection is not limited thereto, and PCI Express (PCIe) (registered trademark), ...

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Abstract

Embodiments of the present invention provide a memory system and control method capable of improving I / O performance. A memory system according to an embodiment includes: a nonvolatile memory including a plurality of blocks each including a plurality of pages; and a controller controlling the nonvolatile memory. When the controller receives a write request specifying a first logical address and a first block number from the host, it determines a first block having the first block number in which data from the host should be written. write data from the host to the first location in the first block. The controller sets the physical address in the first block representing the first position, or any one of the set of the first logical address, the first block number, and the physical address in the first block. or notify the host.

Description

[0001] [Related applications] [0002] This application enjoys the priority of the basic application based on Japanese Patent Application No. 2017-208105 (filing date: October 27, 2017). This application incorporates all the contents of the basic application by referring to this basic application. technical field [0003] Embodiments of the present invention relate to a memory system and a control method including a nonvolatile memory. Background technique [0004] In recent years, memory systems including nonvolatile memories have been widely used. [0005] As one of such memory systems, there is known a solid-state drive (SSD) based on NAND (Not AND) flash memory technology. [0006] Recently, new interfaces between host and memory have started to be proposed. [0007] However, in general, since the control of NAND type flash memory is relatively complicated, when implementing a new interface for improving I / O (Input / Output, input / output) performance, it is necessary to...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F3/06
CPCG06F3/0679G06F3/0644G06F3/064G06F3/061G06F2212/1016G06F2212/152G06F2212/7208G06F12/0246G06F2212/7205G06F2212/7201G06F3/0688G06F3/067G06F3/0616G06F12/10G06F12/06G06F2212/2022G06F2212/7202G06F12/0253G06F3/06
Inventor 吉田英树菅野伸一
Owner 株式会社PANGEA