Unlock instant, AI-driven research and patent intelligence for your innovation.

Overlay mark structure, semiconductor device, and method for detecting overlay errors using acoustic waves

A stacking error, semiconductor technology, applied in semiconductor/solid state device testing/measurement, semiconductor device, analysis of solids using sonic/ultrasonic/infrasonic waves, etc., can solve problems such as imperfection

Active Publication Date: 2021-06-15
TAIWAN SEMICON MFG CO LTD
View PDF10 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this alignment technique is not perfect, and it is desirable to have an alignment technique that provides improved alignment

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Overlay mark structure, semiconductor device, and method for detecting overlay errors using acoustic waves
  • Overlay mark structure, semiconductor device, and method for detecting overlay errors using acoustic waves
  • Overlay mark structure, semiconductor device, and method for detecting overlay errors using acoustic waves

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0075] The present disclosure provides many different embodiments, or examples, for implementing the different features of the disclosure. The following disclosure describes specific examples of various components and their arrangements to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the disclosure describes that a first feature is formed on or over a second feature, it may include embodiments in which the first feature is in direct contact with the second feature, Embodiments may also be included in which additional features are formed between the first and second features such that the first and second features may not be in direct contact. In addition, the same reference signs and / or symbols may be reused in different examples in the following publications. These repetitions are for simplicity and clarity and are not intended to limit a particular relationship between the various embodiments and / or structure...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

An overlay mark structure includes a first periodic structure on a chip, and the first periodic structure includes a first layer of material on the chip. The overmark structure also includes a second periodic structure located in a region of the chip adjacent to the first periodic structure, the second periodic structure including a second layer of material disposed on the chip. The overlay mark structure also includes an acoustic wave emitting device located on the chip and an acoustic wave receiving device located on the chip.

Description

technical field [0001] The present disclosure relates to an overlay marker structure, in particular an overlay marker structure that can detect overlay errors by using acoustic waves. Background technique [0002] In the semiconductor integrated circuit (IC) industry, technological advances in integrated circuit materials and integrated circuit design produce multiple integrated circuit generations, each integrated circuit generation having smaller and more complex circuits than the previous integrated circuit generation. During the development of integrated circuits, the geometric size (eg, the smallest component (or circuit)) that can be produced by the process will decrease, and the functional density (eg: the number of connected components per chip area) will generally increase. This miniaturization process provides advantages by increasing production efficiency and reducing associated costs. This scaling also increases the complexity of integrated circuit technology an...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/544H01L21/66H01L21/68G01N29/04
CPCG03F7/70633G03F7/70641G06T7/001G06T2207/30148G06T7/68
Inventor 李雨青方玉标
Owner TAIWAN SEMICON MFG CO LTD