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A kind of double buried layer mos gate controlled thyristor and preparation method thereof

A thyristor and gate control technology, applied in the field of double buried MOS gate control thyristor and its preparation, can solve the problem of different opening of multiple cells, and achieve the effects of improving hole current density, suppressing output snapback, and improving work reliability.

Active Publication Date: 2022-03-25
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

[0006] The double-buried MOS gate-controlled thyristor and the preparation method provided by the present invention can increase the device turn-on speed, suppress the snapback phenomenon in the turn-on process of the base resistance control thyristor (BRT) and the emitter switch thyristor (EST), and solve the inconsistency of multi-cell turn-on problems, alleviate uneven current distribution, and improve device turn-on reliability

Method used

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  • A kind of double buried layer mos gate controlled thyristor and preparation method thereof
  • A kind of double buried layer mos gate controlled thyristor and preparation method thereof
  • A kind of double buried layer mos gate controlled thyristor and preparation method thereof

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Embodiment Construction

[0041] In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0042] Embodiments of the present invention provide a double buried MOS gate-controlled thyristor, such as image 3 As shown, the thyristor includes:

[0043] Substrate and drift region;

[0044] A double-N buried layer and a surface structure are arranged in the drift region in sequence from bottom to top;

[00...

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Abstract

The invention provides a double-buried MOS gate-controlled thyristor and a preparation method thereof. The double-buried MOS gate-controlled thyristor includes: a substrate and a drift region; a double N buried layer and a surface structure are arranged in the drift region from bottom to top ; The cathode and the grid are arranged on the upper end face of the surface structure, and the anode is arranged on the lower end face of the substrate. The invention can improve the device opening speed, suppress the snapback phenomenon during the opening process of the base resistance control thyristor (BRT) and the emitter switch thyristor (EST), solve the problem of inconsistency in the opening of multiple cells, alleviate the uneven current distribution, and improve the reliability of device opening .

Description

technical field [0001] The invention relates to the technical field of power semiconductors, in particular to a double buried layer MOS gate-controlled thyristor and a preparation method. Background technique [0002] Compared with Insulated Gate Bipolar Transistor (IGBT, Insulated Gate Bipolar Transistor), MOS gated thyristor (MOS gated thyristor: MOS-gated thyristor) has the advantages of low on-resistance, high current density and fast turn-on speed. Fields such as pulsed power have broad application prospects. The MOS gated thyristor mainly includes a thyristor structure composed of four layers of N-P-N-P materials. Through NMOS (Metal Oxide Semiconductor Field Effect Transistor: MOSFET, MetalOxide Semiconductor Field Effect Transistor, N-channel Field Effect Transistor: NMOS) electron current is injected to turn on the positive feedback inside the thyristor. The device is turned on, and the PMOS (P-channel field effect transistor: PMOS) draws the feedback current to in...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/332H01L29/749H01L29/06
Inventor 胡飞宋李梅韩郑生杜寰
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI