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self-adaptive high-speed SAR-ADC conversion time complete utilization circuit and method

A conversion time, adaptive technology, applied in code conversion, analog-to-digital converter, analog-to-digital conversion, etc., can solve the problems of reducing ADC speed and accuracy, short time, wasting area and power consumption, and reducing conversion errors. , high reliability, the effect of improving the conversion rate

Active Publication Date: 2019-06-18
上海胤祺集成电路有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Usually a phase-locked loop is required to generate such a high clock, which wastes significant area and power consumption and increases design complexity
[0003] The conversion time of high-speed SAR-ADC is very short, and the complete utilization of the conversion time is very critical. If the phase-locked loop is not used, the asynchronous ultra-high-speed comparison clock generated inside the commonly used ADC varies greatly with the process, power supply voltage and temperature, resulting in ADC conversion. The time cannot be fully utilized, reducing the speed and accuracy of the ADC
At the same time, the traditional rc calibration method of comparing time cannot satisfy the full utilization of conversion time under various conversion rates

Method used

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  • self-adaptive high-speed SAR-ADC conversion time complete utilization circuit and method

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Embodiment Construction

[0014] Common high-speed ADCs such as figure 1 As shown, the ADC is composed of DAC, comparator, SAR logic circuit, and clock generation circuit. The conversion process of the ADC is roughly divided into three steps. The first step is the sampling mode. After the ADC input clock clk arrives, when the sample is at a high level , the input signal is sampled to the lower plate of the capacitor array of the DAC, and the upper plate of the capacitor is connected to Vcm; the second step is to hold the mode, when clk_vcm is high, the upper plate is disconnected from Vcm, and the lower plate of the capacitor is connected to Vcm; The third step is the charge redistribution mode (comparison mode), the falling edge of clk_vcm generates the rising edge of the first comparison, such as figure 2 As shown in the ADC conversion timing of the comparator, the comparator starts to compare. According to the comparison result, Outp or Outn starts to fall, the clock generation circuit makes the re...

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Abstract

The invention discloses a self-adaptive high-speed SAR-ADC conversion time complete utilization circuit and method. According to the circuit and method for completely utilizing the ADC conversion time, when an ADC enters a maintaining mode, clk _ vcm rises, a trigger DFF1 outputs the sum of the last control bit of a resistor R1 and a control bit needing to be adjusted to the control bit of the current resistor R1, and it is guaranteed that the current comparison frequency is equal to n; the counter is reset after the rising edge of the clk _ vcm is delayed; After entering the comparison mode,the counter counts the current comparison times; For an nbit ADC with redundancy, n times of comparison needs to be carried out, and if m times of comparison are carried out in the previous time, thecurrently needed comparison frequency is Yn = Y (n-1) + m-n. According to the method, the comparison times are counted, and then the comparison times are adjusted in a self-adaptive mode, so that theADC carries out accurate n times of comparison in the whole conversion period, and the conversion error is reduced. Under the condition that the ADC conversion rate is changed, real-time tracking canbe realized, and the conversion rate is improved; In addition, the method is irrelevant to process, power supply voltage and temperature changes and is high in reliability.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an adaptive high-speed SAR-ADC conversion circuit and a method for fully utilizing the conversion time. Background technique [0002] For the commonly used SAR-ADC sampling, the hold and each comparison are driven by an external synchronous clock to nbit SAR-ADC without redundancy. If the sampling rate is Fs, sampling and hold each take up 1 clock cycle, and n comparisons take up For n clock cycles, the ADC clock is at least (n+2)*Fs, and for redundant ADCs, the clock frequency will be higher. For example, for a 20Msps ADC with redundant 17bit, the clock frequency needs to be (17+2)*20=580MHz. Usually, a phase-locked loop is required to generate such a high clock, which wastes significant area and power consumption, and increases design complexity. [0003] The conversion time of high-speed SAR-ADC is very short, and the complete utilization of the conversion time i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/20H03M1/38
Inventor 危长明陈良生罗志国李俊夏建宝杨楠
Owner 上海胤祺集成电路有限公司
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