3D memory device and manufacturing method thereof

Abstract

This application discloses a 3D memory device and a manufacturing method thereof. The 3D memory device includes: a semiconductor substrate; a first array structure located on the semiconductor substrate and including a first gate stack structure; a plurality of first channel pillars penetrating the first gate stack structure and connected with the semiconductor substrate Contact; a first groove extending from the surface of the first array structure to the semiconductor substrate and surrounding the first gate stack structure; and a first sealing ring at least partially covering both side walls of the first groove and connecting with the semiconductor substrate contact. The 3D memory device forms a first sealing ring by covering both side walls of the first groove, which not only improves the problem that gaps are easily formed in the sealing ring during the deposition process, but also achieves a double-layer sealing effect.

Description

technical field [0001] The present invention relates to memory technology, and more specifically, to a 3D memory device and a manufacturing method thereof. Background technique [0002] The improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further increase storage density, memory devices with a three-dimensional structure (ie, 3D memory devices) have been developed. A 3D memory device includes a plurality of memory cells stacked in a vertical direction, which can double the integration level on a wafer per unit area and reduce the cost. [0003] The 3D storage device adopts a stacked structure to provide the gate conductor of the selection transistor and the storage transistor, and uses a sealing ring (Seal Ring, SR) to ...

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Problems solved by technology

[0004] In the prior art, the sealing ring adopts deep groove etching and deposition processes to form a ring structure extending from the surface of the array structure to the semiconductor substrate. Due to the small size of the deep groove, depositing metal tungsten in the deep groove is easy to produce voids. After the grinding process, the voids will be exposed, thereby trapping particles (such as particles containing fluorine elements), which will interfere with subsequent processes and affect the function of 3D memory

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