Structure of static random access memory and formation method thereof

Abstract

The present invention provides a structure of a static random access memory and a formation method thereof. The method comprises the steps of: providing an initial substrate, wherein the initial substrate comprises at least one first region; removing part of the initial substrate of the at least one first region, and forming a substrate, a first fin portion located at the surface of the substrateand a second initial fin portion located at the surface of the substrate, wherein the second initial fin portion and the first fin portion are different in width, part of the first fin portion is configured to form pass-gate transistors, and part of the first fin portion and the second initial fin portion are configured to form pull-down transistors. The static random access memory formed by employing the method is good in performance.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a structure of a static random access memory and a forming method thereof. Background technique [0002] With the continuous development of digital integrated circuits, on-chip integrated memory has become an important part of digital systems. Static Random Access Memory (SRAM) has become an indispensable and important part of on-chip memory due to its advantages of low power consumption and high speed. SRAM can hold data as long as power is supplied to it, rather than constantly refreshing it. [0003] The basic SRAM generally includes six transistors: 2 pull-up transistors (Pull-up transistor, PU), 2 pull-down transistors (Pull-down transistor, PD) and 2 pass-gate transistors (Pass-gate transistor, PG) . In the neural process of SRAM, it is usually necessary to ensure a sufficiently large β ratio (Ipd / Ipg current ratio) to obtain a sufficiently high static noise ...

AI Technical Summary

Problems solved by technology

Therefore, the different requirements for the performance of the pass transistor cause a conflict between the writeability and read stability of the SRAM

[0004]However, prior art SRAM performance is still poor

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