Verification incentive generation method, device, chip verification method and system
A chip and coverage technology, applied in the field of verification, can solve the problems of low chip verification efficiency and difficult to improve coverage, and achieve the effect of accelerated convergence and improved efficiency
Active Publication Date: 2020-01-17
CAMBRICON TECH CO LTD
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[0011] Based on this, it is necessary to address the problem that the coverage rate is difficult to increase after it reaches a certain value, resulting in low chip verification efficiency, and to provide a method for generating verification incentives for chip verification to improve chip verification efficiency.
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[0056]In order to make the purpose, technical solution and technical effect of the present invention clearer, specific embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. It should be clear that "first", "second", etc. in this embodiment are only used to distinguish the described objects, and do not have any sequence or technical meaning.
[0057] Such as figure 1 As shown, a chip verification system according to an embodiment, the system includes: a stimulus generating device 110 , an RTL simulator (Register Transfer level simulation) 120 , a verification model 130 (Reference model), and a first processor 14...
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The invention relates to a verification excitation generation method, a verification excitation generation device, a chip verification method and a chip verification system. The method comprises stepsof obtaining a coverage rate improvement value corresponding to the verification excitation used for verification through deep analysis of the coverage rate data; obtaining a constraint file corresponding to the target verification excitation according to whether the coverage rate increase value reaches a preset threshold value or not, adjusting the constraint condition to obtain a final constraint condition, and finally obtaining the verification excitation according to the final constraint condition. As the verification excitation obtained by the method is obtained according to the target excitation with great influence on coverage rate increase, convergence of the coverage rate of chip verification can be accelerated during RTL simulation, and the efficiency of chip verification is improved.
Description
technical field [0001] The present invention relates to the technical field of verification, in particular to a verification incentive generation method, device, chip verification method, system, storage medium and computer equipment. Background technique [0002] One of the purposes of chip verification is to detect bugs in the programs running on the chip. During chip verification, the RTL emulator (Register Transfer level simulation) and the verification model of the chip verification system execute the verification stimulus generated by the stimulus generation device, output the execution result, and the processor of the chip verification system obtains the coverage data according to the output result, and Determine whether the chip verification is terminated according to whether the obtained coverage data meets expectations. Coverage data is a quantitative indicator used to evaluate the verification process and results. [0003] At present, the mechanisms that generat...
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IPC IPC(8): G06F11/26
CPCG06F11/261
Inventor 不公告发明人
Owner CAMBRICON TECH CO LTD