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Semiconductor processing chamber

A technology for semiconductors and processing chambers, applied in the field of processing chambers

Active Publication Date: 2019-07-09
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, there is a limitation in reducing the time required to form a material layer using various processing chambers separated from each other

Method used

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  • Semiconductor processing chamber
  • Semiconductor processing chamber
  • Semiconductor processing chamber

Examples

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Embodiment Construction

[0017] will refer to Figure 1 to Figure 5 A semiconductor processing chamber according to example embodiments is described. figure 1 is a schematic top view of a semiconductor processing chamber 10 according to an example embodiment, figure 2 is a schematic perspective view of a susceptor 20 and structures related to the susceptor 20 disposed in the semiconductor processing chamber 10, and Figure 3 to Figure 5 is a schematic cross-sectional view of a portion of semiconductor processing chamber 10 according to an example embodiment. exist Figure 3 to Figure 5 middle, image 3 is a schematic cross-sectional view taken along line I-I′ from the first processing region 12 to the third processing region 14 of the semiconductor processing chamber 10 according to an example embodiment; Figure 4 is a schematic cross-sectional view taken along line II-III from the second processing region 13 to the third processing region 14 of the semiconductor processing chamber 10 according ...

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PUM

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Abstract

A semiconductor processing chamber is provided. The semiconductor processing chamber includes a susceptor on which a plurality of wafers are disposed; a showerhead structure opposing the susceptor anddisposed to be spaced apart from the susceptor; a plurality of plates opposing the susceptor and disposed to be spaced apart from the susceptor; and a blocking structure disposed between plates, among the plurality of plates, disposed adjacent to each other, wherein a distance between the showerhead structure and the susceptor is less than a distance between the plurality of plates and the susceptor, and a distance between the blocking structure and the susceptor is less than the distance between the plurality of plates and the susceptor.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of priority from Korean Patent Application No. 10-2017-0170178 filed in the Korean Intellectual Property Office on December 12, 2017, the disclosure of which is incorporated herein by reference in its entirety. technical field [0003] The inventive concept relates to a processing chamber, and more particularly, to a semiconductor processing chamber that simultaneously performs deposition processing and plasma processing. Background technique [0004] In order to increase the degree of integration of semiconductor devices without increasing costs, requirements for various material layers forming semiconductor devices have increased. For example, it is necessary to form thinner layers of material with uniform properties in a shorter period of time. Among material layers used in semiconductor devices, there have been material layers formed using various process chambers separated from...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01J37/32C23C16/455C23C16/458
CPCH01J37/32449H01J37/32908H01J37/32807C23C16/458C23C16/45563H01L21/6719H01L21/68764H01L21/68771H01L21/68742C23C16/4584C23C16/45565C23C16/50H01L21/67017H01L21/683C23C16/45517C23C16/45525C23C16/45544H01J37/32091
Inventor 白承宰南宫铉李泰宗金善政金周妍吹上纪明岩崎征英反田雄太
Owner SAMSUNG ELECTRONICS CO LTD
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