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Hardware unit for performing matrix multiplication with clock gating

A matrix multiplication and hardware technology, applied in the field of hardware units, can solve problems such as matrix multiplication time-consuming

Active Publication Date: 2022-05-13
IMAGINATION TECH LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, matrix multiplication can be time-consuming, especially for large matrices

Method used

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  • Hardware unit for performing matrix multiplication with clock gating
  • Hardware unit for performing matrix multiplication with clock gating
  • Hardware unit for performing matrix multiplication with clock gating

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Embodiment Construction

[0037] The following description is given by way of example to enable a person skilled in the art to make and use the invention. The present invention is not limited to the embodiments described herein, and various modifications to the disclosed embodiments will be readily apparent to those skilled in the art. The embodiments are described by way of example only.

[0038] The hardware performing matrix multiplication may be implemented as a pipeline with multiple pipeline stages. For example, figure 1An example hardware unit 100 for performing matrix multiplication is shown, wherein the matrix multiplication is performed via a plurality of pipeline stages 102 , 104 , 106 , 108 . The first stage 102 (which may be referred to as a multiplier stage) includes a plurality of parallel multipliers 110 that each combine a first data element ( D1 ) of the first set of data elements with a second The data elements (D2) are multiplied to produce a multiplied data element. The first s...

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Abstract

The present disclosure relates to a hardware unit for performing matrix multiplication with clock gating. The present disclosure provides hardware units and methods for performing matrix multiplication via a multi-stage pipeline, wherein storage elements associated with one or more stages of the pipeline are based on data known to have a value of zero or can be considered to have a value of zero elements and / or parts thereof are clocked. In some cases, the storage elements may be clocked on a per data element basis based on whether the data element has a value of zero or may be deemed to have a value of zero. In other cases, storage elements may be clocked based on the bit width of the data element on a partial element basis. For example, if the bit width of a data element is less than the maximum bit width of the data element, a portion of the bits associated with the data element may be considered to have a value of zero and a portion of the storage elements associated with the data element may not be clocked.

Description

technical field [0001] The present disclosure relates to matrix multiplication, and more particularly, to hardware units with clock gating for performing matrix multiplication. Background technique [0002] Matrix multiplication is the multiplication of a first matrix A and a second matrix B to produce a third matrix C. If A is an a x b matrix and B is a b x c matrix like this: [0003] [0004] [0005] Then the result of the matrix multiplication is the matrix C of a x c as follows: [0006] [0007] where each element C of matrix C ij Computed by multiplying the elements in row i of matrix A by the elements in column j of matrix B and summing the results, as shown in equation (1): [0008] [0009] Matrix multiplication is a key operation in many applications. For example, matrix multiplication can be used to compute the convolution of input data and weights in a deep neural network (DNN). However, matrix multiplication can be time-consuming, especially f...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F7/544G06F17/16
CPCG06F7/5443G06F17/16G06N3/063G06N3/045G06F7/523G06N20/00G06F7/50G06F9/3824G06F9/3869
Inventor 克里斯·马丁阿祖拉·普利梅诺
Owner IMAGINATION TECH LTD