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Error correction code scrub scheme

An error correction and error technology, applied in the field of error correction code erasure scheme, can solve the problems of increasing time, error, ECC operation determination and correction unit error, etc.

Pending Publication Date: 2019-07-19
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although this process can determine and correct single bit errors associated with data bits, the memory array must contain sufficient storage to accommodate each of the parity and data bits
Additionally or alternatively, the necessary read and write processes can result in additional power consumption and increased time for ECC operations to determine and correct single-bit errors, especially during ECC erase operations

Method used

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Embodiment Construction

[0018] For various memory processes, one or more data bits and one or more parity bits are typically encoded and written to the memory array. The data bits and parity bits can then be read from the memory array through a decoding process, and a single bit error corresponding to a data bit can be determined. Single-bit errors can then be corrected and can be encoded and rewritten to the memory array. Because the data has been corrected, and because the data can be combined with "new" data (eg, additional user data), the data must be encoded before being written to the memory array. This process typically requires the memory array to be sized accordingly (eg, to enable it to store additional encoded data), and is time and power consuming. Thus, a memory device capable of omitting aspects of the encoding process in some cases can reduce the amount of storage space consumed by encoded data in the memory array, can result in improved timing of ECC operations, and reduced power con...

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Abstract

The invention relates to an error correction code scrub scheme. Methods, systems, and devices for an error correcting code scrub scheme are described. A memory device may correct an error associated with a first data bit or a first parity bit of a plurality of data bits and a plurality of parity bits, respectively. The memory device may correct the error by reading each of the plurality of data bits and the plurality of parity bits from a memory array, and determining that an error associated with a single bit exists. The memory device may then correct the determined single-bit error, and maywrite the corrected bit directly back to the memory array.

Description

[0001] cross reference [0002] This patent application claims priority to U.S. Patent Application Serial No. 15 / 839,617, filed December 12, 2017, by Kwak, entitled "Error Correction Code Scrub Scheme" , assigned to the present assignee and expressly incorporated herein by reference in its entirety. technical field [0003] The technical field relates to an error correction code erasure scheme. Background technique [0004] The following generally relates to operating memory arrays and more specifically to an error correction code erasure scheme. [0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, a binary device has two states, typically represented by a logic "1" or a logic "0." In other systems, more than two states may be stored. To access stored in...

Claims

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Application Information

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IPC IPC(8): G11C29/42
CPCG11C29/42G11C7/1006G11C11/4076G11C11/4099G11C2211/4062G11C2029/0409G11C2029/0411G06F11/106G11C11/221G11C29/52G06F11/1068G11C11/406
Inventor 钟太·郭
Owner MICRON TECH INC