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High speed data weighted averaging architecture

A weighted average, data technique, applied in the field of signal processing

Pending Publication Date: 2019-07-23
STMICROELECTRONICS SRL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The performance of the circuit is also adversely affected by interleaving using multiple parallel paths

Method used

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Embodiment Construction

[0018] In the following detailed description and drawings, specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to those skilled in the art that, in some cases, the present disclosure may be practiced without these specific details. In other instances, well-known elements have been shown in schematic or block diagram form in order not to obscure the disclosure in unnecessary detail. Additionally, for the most part, specific details, etc. have been omitted, since such details are not deemed necessary to gain a complete understanding of the present disclosure, and are believed to be within the understanding of one of ordinary skill in the relevant art.

[0019] now refer to image 3 , image 3 A block diagram of a data weighted averaging (DWA) circuit 200 is shown. The circuit includes a data bus 202 which carries a multi-bit input data word DT in thermometer encoded format . In one example, N-1...

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Abstract

The embodiment of the invention relates to a high speed data weighted averaging architecture. Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operationof a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.

Description

technical field [0001] The present disclosure relates to the field of signal processing, and in particular, to a data weighted averaging architecture. Background technique [0002] For high-speed data converters, the data weighted average (DWA) algorithm is usually used as a solution to realize dynamic element matching (DEM). figure 1 A comparison of the operation of data converter 102 without DWA and data converter 104 with DWA is illustrated. A data word 110 is received and processed by converter circuitry to actuate an output element (OE) of a digital-to-analog converter (DAC). In this example, the DAC includes seven output elements. [0003] For data converter 102 , data word 110 is decoded by thermometer decoder 120 to generate control signal 122 whose data bits selectively actuate output element 124 . If the data word has a value of 3 (binary format <0,1,1>), the thermometer decoder 120 decodes the word to generate a value of <1,1,1,0,0,0,0> A seven-bit...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/06
CPCH03M1/0665H03M1/46H03M7/14H03M1/66H03M7/165H03M3/468
Inventor A·巴尔R·辛格
Owner STMICROELECTRONICS SRL