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Method for designing chip using embedded command

An embedded and embedded control technology, applied in computer-aided design, CAD circuit design, calculation, etc., can solve problems such as not allowing modification, achieve good practical performance, and save communication time

Active Publication Date: 2019-08-09
深圳市酷童小样科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, many third-party IPs are not allowed to be modified or require a relatively long period to complete the modification

Method used

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  • Method for designing chip using embedded command
  • Method for designing chip using embedded command
  • Method for designing chip using embedded command

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0047] A method for designing a chip using embedded commands. The method for designing a chip using embedded commands includes the following steps:

[0048] S1: Determine the code in top module1.rest_wrapper that needs to control the logic synthesis result;

[0049] S2: Add the embedded command to the top-level module, the embedded command contains the code label determined in S1, so as to achieve the purpose of controlling the logic synthesis tool;

[0050] S3: Read the code and design code containing embedded commands into CAD / EDA software;

[0051] S4: When the CAD / EDA software compiles embedded control statements, if you see the embedded control statements in the top-level module, it will automatically map the embedded control statements at the top-level to the modules that need to be controlled inside the module to control The synthesis tool completes the internal logic synthesis tool of the module according to the embedded control sentence.

Embodiment 2

[0053] A method for designing a chip using embedded commands. The method for designing a chip using embedded commands includes the following steps:

[0054] S1: Determine the code in top module1.rest_wrapper that needs to control the logic synthesis result;

[0055] S2: Add the embedded command to the top-level module, the embedded command contains the code label determined in S1, so as to achieve the purpose of controlling the logic synthesis tool;

[0056] S3: Read the code and design code containing embedded commands into CAD / EDA software;

[0057] S4: When the CAD / EDA software compiles embedded control statements, if you see the embedded control statements in the top-level module, it will automatically map the embedded control statements at the top-level to the modules that need to be controlled inside the module to control The synthesis tool completes the internal logic synthesis tool of the module according to the embedded control sentence. In step S3, the CAD / EDA software adds...

Embodiment 3

[0059] A method for designing a chip using embedded commands. The method for designing a chip using embedded commands includes the following steps:

[0060] S1: Determine the code in top module1.rest_wrapper that needs to control the logic synthesis result;

[0061] S2: Add the embedded command to the top-level module, the embedded command contains the code label determined in S1, so as to achieve the purpose of controlling the logic synthesis tool;

[0062] S3: Read the code and design code containing embedded commands into CAD / EDA software;

[0063] S4: When the CAD / EDA software compiles embedded control statements, if you see the embedded control statements in the top-level module, it will automatically map the embedded control statements at the top-level to the modules that need to be controlled inside the module to control The synthesis tool completes the internal logic synthesis tool of the module according to the embedded control sentence. In step S3, the CAD / EDA software adds...

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Abstract

The invention discloses a method for designing a chip using an embedded command. The method comprises the following operation steps: S1, determining codes in a module top module1.rest_wrapper needingto control a logic comprehensive result; S2, adding the embedded command into a top layer module, the embedded command comprising the code mark number determined in the step S1, and therefore the purpose of controlling the logic comprehensive tool being achieved; S3, the code containing the embedded command and the design code are read into CAD / EDA software; S4, when the CAD / EDA software compilesthe embedded control statement, compiling the embedded control statement; if the embedded control statement is seen in the top layer module, automatically mapping the embedded control statement on thetop layer into a module needing to be controlled in the module, so that a comprehensive tool is controlled to complete a logic comprehensive tool in the module according to the embedded control statement. According to the method for designing the chip using the embedded command provided by the invention, CAD / EDA software is designed on the top layer of the chip, a required circuit is comprehensively generated according to the requirements of a designer, the communication time is saved, iteration is designed, and the method has good practical performance.

Description

Technical field [0001] The invention relates to a method for designing a control chip, in particular to a method for designing a chip using embedded commands. Background technique [0002] In Soc (system on chip) chip design, different modules need to be integrated. One is the company's internal design and some are provided by third-party IP vendors. [0003] Alarms such as ARM Cortex series processor cores, Synopsys’ USB, PCIE bus modules, etc. Chip design companies can use these third-party modules to quickly complete SOC design, avoid risks, and quickly launch chip products on the market. In the SoC design process, it is usually necessary to control the chip synthesis. One of the scenarios is to control the chip synthesis to use multiple selectors instead of combinational logic to avoid glitches and cause unnecessary subsequent circuits. In the design process, it is usually necessary to control the chip synthesis. One of the scenarios is to control the chip synthesis to use mu...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/39Y02P90/02
Inventor 肖有军孙艳玲高琼吕琴
Owner 深圳市酷童小样科技有限公司
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