Chip package structure
A chip packaging structure and chip technology, applied in the direction of electrical components, electrical solid devices, circuits, etc., to achieve the effect of increasing the contact area, achieving compatibility, and neutralizing thermal deformation
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[0045] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.
[0046] The chip packaging structure of the present invention comprises a circuit substrate, a chip on the circuit substrate, a packaging flat panel above the chip, and a sealing dam is used to seal the circuit substrate and the packaging flat panel.
[0047] The following is attached Figure 1-11 The present invention will be described in further detail with specific examples. It should be noted that the drawings are all in a very simplified form, using imprecise scales, and are only used to facilitate and clearly achieve the purpose of assisting in describing the...
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