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Hardware acceleration method

A hardware acceleration and addition technology, applied in digital data processing components, instruments, electrical digital data processing, etc., can solve the problems of long task time, affecting the data transmission rate of the upper computer, and increasing the task cycle time of the airborne software. The effect of reducing task cycle time and resource overhead

Active Publication Date: 2019-08-20
XIAN AVIATION COMPUTING TECH RES INST OF AVIATION IND CORP OF CHINA
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The airborne software can only perform serial computing tasks, and the calculation of a large number of analog acquisition results will inevitably occupy a long time for the airborne software task, which will increase the task cycle time of the airborne software and affect the data transmission rate of the upper computer

Method used

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  • Hardware acceleration method

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Embodiment 1

[0026] The technical solution of the present invention: a hardware acceleration method suitable for linear fitting of airborne products with more analog quantity acquisition, characterized in that: the method is implemented based on the architecture of FPGA+AD, specifically including analog quantity acquisition, Floating-point data normalization, linear fitting parameter loading, floating-point number multiplication and floating-point number addition are five parts. The five parts in the method are all implemented based on FPGA, and the purpose is to take advantage of the advantages that FPGA logic can perform parallel operations. Complete all analog acquisition results in the airborne product in an automatic cycle, and store the results in registers. The host computer software does not need to participate in the process of analog quantity acquisition and linear fitting operation, it only needs to read the data of the corresponding register when the analog quantity acquisition ...

Embodiment 2

[0034] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0035] figure 1 It is a structural block diagram of a linear fitting hardware acceleration method suitable for airborne products with many analog acquisitions. refer to figure 1 As shown, the method is implemented based on the architecture of FPGA+AD, and specifically includes five parts such as analog quantity acquisition, floating-point data normalization, linear fitting parameter loading, floating-point number multiplication and floating-point number addition, and five parts in the method Each part is implemented based on FPGA, the purpose is to take advantage of the parallel operation of FPGA logic, automatically complete all the analog acquisition results in airborne products, and store the results in registers. The host computer software does not need to participate in the process of analog quantity acquisition and linear fitting operat...

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Abstract

The invention provides a hardware acceleration method, and the method comprises the steps: collecting an analog quantity, wherein the data format of the analog quantity is a binary format; convertingthe data format of the analog quantity into a floating-point number; and according to preset parameters, performing parallel operation on floating-point number multiplication and floating-point numberaddition, and obtaining a calculation result.

Description

technical field [0001] The invention belongs to the technical field of digital circuits, in particular to a hardware acceleration method for linear fitting. Background technique [0002] Analog quantity acquisition is an indispensable data source in the airborne computer system, especially in complex electromechanical systems, there are a lot of analog quantity signal acquisition. Usually in the FPGA, only the data collected by the AD conversion chip is stored in the register or stored in the RAM generated by the FPGA, and the onboard software of the host computer completes the reading of the data and calculates the collection result. Airborne software can only perform serial computing tasks, and the calculation of a large number of analog acquisition results will inevitably occupy a long time for the airborne software task, which will increase the task cycle time of the airborne software and affect the data transmission rate of the upper computer. Contents of the inventio...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/575
CPCG06F7/575
Inventor 肖鹏呼明亮屈盼让孙少华蔡晓乐韩佳玮
Owner XIAN AVIATION COMPUTING TECH RES INST OF AVIATION IND CORP OF CHINA
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