System for realizing PCIe bandwidth automatic allocation in server system

Abstract

The invention provides a system for realizing PCIe bandwidth automatic allocation in a server system. The system comprises a mainboard, a mainboard connector, a hard disk backboard and / or a Riser card; the PCH on the mainboard distinguishes whether the downlink connection is a hard disk backboard or a Riser card through a DIS _ BP _ RISER signal; the PCH on the mainboard distinguishes whether thex8 bandwidth is allocated to the x8 bandwidth or the x8 bandwidth and other interfaces form the x16 bandwidth through a DIS _ X8 _ X16 signal; and two pins on the mainboard connector are respectivelycommunicated with the hard disk back plate and the Riser card through a DIS _ BP _ RISER signal and a DIS _ X8 _ X16 signal. According to the method, the functions of the connection signals are redefined, BP _ TYPE is multiplexed on the Slimline connector, the number of the signals used for PCIe bandwidth automatic distribution is solidified, limitation of the number of the board cards and the number of related pins is avoided, the board cards are separated, and binding of the related signals and the bandwidth is achieved.

Description

technical field [0001] The invention belongs to the technical field of PCIe bandwidth design of a server system, in particular to a system for realizing automatic allocation of PCIe bandwidth in a server system. Background technique [0002] In the server system, the main board and different types of sub-cards are matched together to realize various functions of the system; on the main board and sub-card side, PCIe high-speed bus is generally used to complete high-speed signal transmission. PCIe belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices allocate exclusive channel bandwidth and do not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliable transmission, hot swapping and quality of service ( QOS) and other functions. There are many kinds of devices that can be connected to the PCIe bus, including external cards such as hard disks, network cards, and SAS / RAID cards. ...

AI Technical Summary

Problems solved by technology

The number of riser ID bits is limited by the number of GPIO pins of the PCH and the number of available pins of the interconnection interface. On the motherboard, the PCH collects riser IDs from various PCIe interfaces. The large number of signals will lead to insufficient number of PCH GPIO pins. ;Secondly, in a complex system, the signals of the interconnection interface are complex, which will lead to insufficient number of connector pins

The existing technical solution is limited to the situation where there are few configuration types and simple topology. In a complex system, the same PCIe interface may be connected to the riser card and the hard disk backplane at the same time. However, the existing technical solution cannot distinguish the downlink connection through the riser ID. The backplane of the hard disk is still a riser card, so the automatic allocation of PCIe bandwidth cannot be realized

The existing technical solution is not flexible enough, and the new board cannot support it

As mentioned in Article 1 above, the actual number of riser cards should be referred to when designing the riser ID in the early stage. For example, if the design is a 2-digit riser ID, the interface can support up to 4 riser cards, and subsequent new boards cannot support it, and the solution is not enough flexible

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