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Message processing method and device

A message processing and message technology, applied in the field of network communication, can solve the problems of extracting quintuple, unable to exert the advantages of multi-core CPU parallel processing, unable to add messages, etc.

Active Publication Date: 2019-11-26
HANGZHOU DPTECH TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in some cases, remark information may be added to a certain position in the message, which destroys the original information structure in the message, causing the position of the quintuple in the message to change, causing the network controller to fail to accurately If the quintuple is extracted from the message, the message cannot be added to the matching message receiving queue, which leads to the inability to take advantage of the parallel processing of the multi-core CPU.

Method used

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Examples

Experimental program
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Embodiment 1

[0037] image 3 It is a schematic diagram of the principle of a multi-core CPU receiving a message through an FPGA chip provided in this embodiment, such as image 3As shown, a multi-core CPU and an FPGA chip are included, wherein the multi-core CPU includes N CPU cores, and N is a natural number greater than 1; the quintuple information contained in the message that different CPU cores of the multi-core CPU are responsible for processing is different; The FPGA chip maintains N message receiving queues; the N message receiving queues are in one-to-one correspondence with the N CPU cores, and the message receiving queues can be allocated by the multi-core CPU according to the number of cores of the multi-core CPU when the device is initialized For the FPGA chip; for each CPU core, the CPU core can obtain a message from the message receiving queue corresponding to the CPU core maintained by the FPGA chip for processing by accessing the FPGA chip; The chip has an Ethernet port a...

Embodiment 2

[0060] Figure 6 It is a schematic diagram of the principle of a multi-core CPU receiving a message through an FPGA chip and sending a message through a network controller provided in this embodiment, as shown in Figure 6 shown in Figure 5 On the basis of the shown architecture, the device also includes a network controller; the switch chip also includes a third-type Ethernet port connected to the Ethernet port of the network controller; the network controller maintains N messages Sending queue; the N message sending queues correspond to N CPU cores one by one, and the message sending queue can be assigned to the network controller by the multi-core CPU according to the number of cores of the multi-core CPU when the device is initialized; each CPU core A network controller may be accessed to insert a message into a message sending queue corresponding to the CPU core in the network controller. After the FPGA chip receives the message from the Ethernet port, it extracts the ...

Embodiment 3

[0077] Figure 8 It is a schematic diagram of the principle of a multi-core CPU receiving and sending messages through an FPGA chip provided in this embodiment. Such as Figure 8 As shown, on the basis of the second embodiment, the network controller is replaced by an FPGA chip, that is, the FPGA chip also maintains N message sending queues. The N message sending queues are in one-to-one correspondence with the N CPU cores, and the message sending queues can be allocated to the FPGA chip by the multi-core CPU according to the number of cores of the multi-core CPU when the device is initialized; each CPU core can access the The FPGA chip inserts a message into the message sending queue corresponding to the CPU core in the FPGA chip. The main difference between Embodiment 3 and Embodiment 2 is that the task of maintaining the message sending queue is also performed by the FPGA chip. Embodiment 3 can be understood by referring to the description of Embodiment 2 above, and will ...

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Abstract

The invention discloses a message processing method and device. The method is applied to equipment comprising a multi-core CPU and a field programmable gate array FPGA chip, and comprises the steps: enabling the FPGA chip to receive a to-be-processed message through an Ethernet port of the FPGA chip, wherein remark information is added to the to-be-processed message; analyzing and extracting quintuple information from the message to be processed based on a message analysis logic built in an FPGA chip; determining a message receiving queue matched with the message to be processed as a target message receiving queue according to the extracted quintuple information; and adding the to-be-processed message to the target message receiving queue, so as to enable a CPU core corresponding to the target message receiving queue to receive the to-be-processed message. Compared with the prior art, the advantage of parallel processing of the multi-core CPU can still be exerted when the multi-core CPU receives the message of which the quintuple information cannot be correctly identified.

Description

technical field [0001] The present application relates to the technical field of network communication, and in particular to a message processing method and device. Background technique [0002] Currently, a device installed with a multi-core central processing unit (Central Processing Unit, CPU) generally receives a message through a network controller for processing. Based on the advantages of multi-core CPU parallel processing, different CPU cores can process messages with different quintuples (source IP, destination IP, protocol number, source Port, destination Port); usually each CPU core corresponds to a message receiving Queues and a message sending queue, all message receiving queues and sending queues are maintained by the network controller. That is, when the network controller receives a message, it will add the message to the corresponding message receiving queue according to the five-tuple extracted from the message, and the CPU core responsible for processing ...

Claims

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Application Information

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IPC IPC(8): H04L12/861H04L12/933H04L12/935G06F9/50H04L49/111
CPCH04L49/3009H04L49/90H04L49/10G06F9/5027
Inventor 阎鑫淼任红军
Owner HANGZHOU DPTECH TECH
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