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Selective element and storage device

A technology for selecting devices and storage devices, which is applied in the direction of information storage, static memory, electric solid-state devices, etc., can solve the problems of reduced reliability of storage devices and degradation of cycle characteristics of selected devices, so as to improve reliability, reduce heat generation, reduce effect of change

Inactive Publication Date: 2019-12-06
SONY SEMICON SOLUTIONS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the resistive variable memory, a relatively large current needs to flow in order to change the resistance state of the memory device, but the magnitude of the current becomes a cause of reduced reliability of the memory device
This is because most of the current flowing in the select device is converted into heat, degrading the cycle characteristics of the select device

Method used

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  • Selective element and storage device
  • Selective element and storage device
  • Selective element and storage device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0045] figure 1 A cross-sectional configuration of a selection device (selection device 10 ) according to the first embodiment of the present disclosure is schematically shown. For example, the selection device 10 selectively causes the arrangement to have Figure 4 An optional memory device (memory device 40 ) among a plurality of memory devices in a memory cell array (memory cell array 100 ) of a so-called cross-point array structure shown in FIG. The selection device 10 is coupled in series with the storage device 40, and has an OTS (two-way threshold switching) layer 13 (semiconductor layer) arranged between the lower electrode 11 (first electrode) and the upper electrode 12 (second electrode) opposite to each other. structure, which will be described in detail later. In the selection device 10 according to the present embodiment, as figure 2 As shown in , a thermal bypass layer 14 (first thermal bypass layer) is disposed around the OTS layer 13 .

[0046] (1-1. Selec...

no. 3 example

[0127] Figure 17 is a perspective view of the OTS layer 33 and the thermal bypass layer 34 included in the selection device (selection device 30 ) according to the third embodiment of the present disclosure. As in the selection device 10 in the first embodiment described above, the selection device 30 selectively makes, for example, a plurality of memory devices arranged in a memory cell array having a cross-point array structure (for example, the memory cell array 100) The optional storage device (storage device 40) of the The selection device 30 is coupled in series with the memory device 40, and the OTS layer 33 is disposed between the lower electrode 11 and the upper electrode 12 that are opposed to each other. The present embodiment differs from the first and second embodiments in that the OTS layer 33 extends in one direction (for example, in the direction of the word line WL or the direction of the bit line BL), and on both sides of the extended OTS layer 33 A therma...

Deformed example 1

[0132] Figure 18 A cross-sectional configuration of a selection device (selection device 60 ) according to a modified example of the present disclosure is schematically shown. As in the selection device 10 in the above-described first embodiment, the selection device 60 selectively causes, for example, a plurality of memory devices arranged in a memory cell array (for example, the memory cell array 100 ) having a cross-point array structure The optional storage device (storage device 40) of the As in the selection device 10, the selection device 60 according to the present modification includes a thermal bypass layer 64A around the OTS layer 13 provided between the lower electrode 11 and the upper electrode 12 facing each other, and includes The thermal bypass layer 64B (second thermal bypass layer) inside the OTS layer 13 (for example, in the central portion of the OTS layer 13).

[0133] Both thermal bypass layer 64A and thermal bypass layer 64B have properties similar to...

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Abstract

A selective element according to one embodiment of the present disclosure is provided with: a first electrode; a second electrode disposed opposite to the first electrode; a semiconductor layer that is provided between the first electrode and the second electrode and that includes at least one chalcogen element selected from tellurium (Te), selenium (Se), and sulfur (S) and includes at least one first element selected from boron (B), aluminum (Al), gallium (Ga), phosphorus (P), arsenic (As), carbon (C), germanium (Ge), and silicon (Si); and a first heat bypass layer that has higher thermal conductivity than the semiconductor layer and that is provided on at least a part of the periphery of the semiconductor layer, between the first electrode and the second electrode.

Description

technical field [0001] The present disclosure relates to a selection device including a semiconductor layer including a chalcogenide between electrodes and a memory device including the selection device. Background technique [0002] In recent years, there has been a demand to increase the capacity of nonvolatile memories for data storage represented by resistive random access memories such as ReRAM (Resistive Random Access Memory). In contrast, a typical memory device adopts a cross-point memory cell array structure in which a plurality of memory cells are arranged on a plane or a stacked memory cell array structure in which a plurality of memory cells are stacked in a direction perpendicular to a plane, thereby achieving an increase in capacity. [0003] Each memory cell typically includes two devices, a storage device and a select device. In a resistive variable memory such as ReRAM, writing, reading, or erasing of information is performed by changing the electrical char...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8239H01L27/105H01L45/00H01L49/00
CPCH01L27/105G11C13/003G11C2213/76G11C13/0004G11C11/1659H10B63/24H10B61/10H10B63/80H10B99/00H10N70/821H10N70/841H10N70/881H10N50/10G11C5/063H10B63/84H10B61/00H10N70/231H10N70/882H10N70/884H10N70/8616
Inventor 五十岚实曾根威之野野口诚二清宏彰大场和博
Owner SONY SEMICON SOLUTIONS CORP