Highly Parallel Computing System and Its Instruction Scheduling Method

Abstract

A high-parallel computing system and its instruction scheduling method are proposed. The computing system includes: an instruction reading and distributing module, which is used to read multiple categories of instructions in a specific order, and distributes the obtained instructions to corresponding functional modules according to categories; an internal cache; each of a plurality of functional modules that sequentially execute the instructions of this category distributed by the instruction reading and distribution module and read the required data from the internal cache; and wherein the specific sequence is passed by The above instructions are topologically sorted according to the directed acyclic graph composed of categories and dependencies. Therefore, based on topologically sorting the directed acyclic graph constructed according to the instruction category and dependency relationship to obtain values, deadlocks caused by instruction dependencies can be avoided through relatively simple operations. Preferably, the above sorting can be implemented in the instruction compilation stage, thereby further reducing the resource consumption of the computing system itself.

Description

technical field [0001] The present invention relates to the field of high-parallel computing, and more specifically, to a high-parallel computing system, an instruction scheduling method thereof, and a corresponding compiling method. Background technique [0002] Neural Network (Neural Network) has become a research hotspot in the field of image recognition in recent years. The trained neural network model can be used in many fields such as image classification, object recognition and saliency detection. In recent years, the neural network model has shown a trend of increasing computing scale and increasing complexity. The use of traditional CPU platforms has been unable to meet its practical requirements. Therefore, using heterogeneous computing platforms such as FPGA, GPU, and ASIC to design neural network accelerators has become a new research hotspot. Among them, compared with the GPU platform, FPGA and ASIC can realize more flexible hardware architecture and higher co...

AI Technical Summary

Problems solved by technology

In recent years, the neural network model has shown a trend of increasing computing scale and increasing complexity. The use of traditional CPU platforms has been unable to meet its practical requirements.

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