Band-gap reference circuit

Abstract

The invention discloses a band-gap reference circuit which comprises a main circuit used for outputting reference current, a starting module used for starting the main circuit, an output module used for outputting band-gap reference voltage of a required specification according to the reference current provided by the main circuit, and a delay control module used for collecting an overshoot signalgenerated by the main circuit in a starting stage and controlling the output module to perform stable output according to the acquired overshoot signal. According to the invention, when the overshootsignal generated by the main circuit in the starting stage is sampled by the delay control module and when the time delay output module is controlled to perform time delay on the sampling of the maincircuit, the time delay time is controllable, then the output module can be controlled to perform sampling after the overshoot signal passes, so the overshoot of output voltage can be weakened or eliminated, and the voltage output of the output module is enabled to be stable.

Description

technical field [0001] The invention relates to the field of circuit technology, in particular to a bandgap reference circuit. Background technique [0002] In a conventional bandgap reference circuit, an overshoot occurs during the establishment of the output voltage Vref. Taking the field of NORFLASH (that is, non-volatile flash memory technology) as an example, the common erasing method of NOR FLASH needs to apply a negative pressure to WL. The negative pressure is generated by the negative charge pump inside the chip, and the size is based on the multiple of Vref. -7 times as an example, that is, the WL voltage is -8.4v when erasing, at this time the VDS of the internal levelshift MOS tube is (3.3-(-8.4))=11.7v, in the safe working range (the process determines the drain and source The punch-through voltage is 12.5v); if the overshoot is 0.3v at this time, the VDS of the levelshift MOS is 13.8v, which is greater than the punch-through voltage, which will cause irreversi...

AI Technical Summary

Problems solved by technology

Taking the field of NORFLASH (that is, non-volatile flash memory technology) as an example, the common erasing method of NOR FLASH needs to apply a negative pressure to WL. The negative pressure is generated by the negative charge pump inside the chip, and the size is based on the multiple of Vref. -7 times as an example, that is, the WL voltage is -8.4v when erasing, at this time the VDS of the internal levelshift MOS tube is (3.3-(-8.4))=11.7v, in the safe working range (the process determines the drain and source The punch-through voltage is 12.5v); if the overshoot is 0.3v at this time, the VDS of the levelshift MOS is 13.8v, which is greater than the punch-through voltage, which will cause irreversible damage to the chip, and NOR FLASH usually requires 100K erase operation The performance does not change between, so it is unacceptable for NOR FALSH

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