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Dynamic latch, data arithmetic unit, chip, computing power board and computing equipment

A dynamic latch and data technology, applied in the direction of voltage/temperature change compensation, reliability improvement and modification, etc., can solve the problems of data loss, data dynamic leakage, etc., and achieve the effect of improving stability, enhancing security and accuracy.

Pending Publication Date: 2020-01-14
HANGZHOU CANAAN INTELLIGENCE INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the cut-off state of the tri-state inverter 101, when the data at the input terminal D changes, the data at the node S0 is prone to dynamic leakage, resulting in the loss of the temporarily stored data

Method used

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  • Dynamic latch, data arithmetic unit, chip, computing power board and computing equipment
  • Dynamic latch, data arithmetic unit, chip, computing power board and computing equipment
  • Dynamic latch, data arithmetic unit, chip, computing power board and computing equipment

Examples

Experimental program
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Embodiment 1

[0063] figure 2 It is a schematic diagram of a circuit structure of a dynamic latch according to an embodiment of the present invention. Such as figure 2 As shown, the dynamic latch 200 includes an input terminal D, an output terminal Q, a clock signal terminal CKN, a clock signal terminal CKP, a data latch unit 201 , a data holding unit 202 and a leakage compensation unit 203 . The data latch unit 201 and the data holding unit 202 are connected in series between the input terminal D and the output terminal Q, and a node S0 is formed between the data latch unit 201 and the data holding unit 202 . The leakage compensation unit 203 is electrically connected between the node S0 and the input terminal D. As shown in FIG. Among them, the input terminal D is used to input data, the output terminal Q is used to output the data input by the input terminal D, the clock signal terminal CKN and the clock signal terminal CKP are used to provide the clock signal CKN and the clock signa...

Embodiment 2

[0076] image 3 It is a schematic diagram of a circuit structure of a dynamic latch according to another embodiment of the present invention. Such as image 3 shown, with figure 2 The difference of the illustrated embodiment is that in this embodiment, in the leakage compensation unit 203 , the gate terminals of the PMOS transistor 203P and the NMOS transistor 203N are connected in parallel and electrically connected to the input terminal D. As shown in FIG.

[0077] Since the gate terminals of the PMOS transistor 203P and the NMOS transistor 203N are also electrically connected to the input terminal D, driven by a signal of the same level, the PMOS transistor 203P and the NMOS transistor 203N will not be turned on at the same time, and only one of them will be turned on. state, the other is in cutoff state. For example, when the potential of the input terminal D is at a high level, the PMOS transistor 203P is in an off state, and the NMOS transistor 203N is in a conductiv...

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Abstract

The invention provides a dynamic latch, a data operation unit, a chip, a computing power board and computing equipment. The dynamic latch comprises an input end which is used for inputting data; an output end which is used for outputting the data; a clock signal end which is used for providing a clock signal; a data latch unit which is used for latching the data under the control of the clock signal; a data maintaining unit which is used for maintaining the data transmitted by the data latch unit. wherein the data latch unit and the data holding unit are connected in series between the input end and the output end, and a node is arranged between the data latch unit and the data holding unit; and an electric leakage compensation unit, wherein the electric leakage compensation unit is electrically connected between the input end and the node. The dynamic leakage current of the node can be effectively compensated, and the safety and accuracy of data are improved.

Description

technical field [0001] The invention relates to a storage device controlled by a clock, in particular to a dynamic latch applied in large-scale data computing equipment, a data computing unit, a chip, a power board and computing equipment. Background technique [0002] Dynamic latches are widely used and can be used as digital signal registers. figure 1 It is a circuit structure diagram of an existing dynamic latch. Such as figure 1 As shown, the dynamic latch 100 includes a tri-state inverter 101 and an inverter 102 connected in series between the input terminal D and the output terminal Q. The node S0 is formed between the tri-state inverter 101 and the inverter 102. The tri-state inverter 101 is controlled by two inverted clock signals CKN and CKP. When CKP is "0", CKN is "1", The three-state inverter 101 is turned on, and the data at the input terminal D is transmitted to the output terminal through the three-state inverter 101 and the inverter 102; when CKN is "0", C...

Claims

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Application Information

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IPC IPC(8): H03K19/003
CPCH03K19/00369
Inventor 刘杰尧张楠赓吴敬杰马晟厚
Owner HANGZHOU CANAAN INTELLIGENCE INFORMATION TECH CO LTD
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