Semiconductor package

Abstract

A semiconductor package includes a package substrate, a flip chip coupled to the package substrate, an interposer stacked on the flip chip and including a first terminal and a second terminal at an upper surface thereof, a bonding wire which connects the first terminal and the package substrate and a mold layer which covers the interposer, the flip chip and the bonding wire. The mold layer has a signal hole which exposes the second terminal, and at least one dummy hole spaced apart from the signal hole on an upper surface of the interposer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2018-0079925 filed with the Korean Intellectual Property Office on July 10, 2018, the disclosure of which is incorporated herein by reference in its entirety. technical field [0002] The inventive concept relates to a semiconductor package. Background technique [0003] The semiconductor industry is constantly trying to miniaturize and reduce the thickness and weight of semiconductor products while maintaining a high degree of product integration. For this reason, various types of packages having component stacks mounted on a substrate have been developed, and their application and use are gradually increasing. [0004] However, the stacked components of the package include various materials with different coefficients of thermal expansion. Thus, during the manufacturing process (for example, when forming the mold layer that encapsulates the component on the substrate), warpage in which the package...

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Problems solved by technology

Such warping can significantly reduce package reliability

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