Layout graph filling method

Abstract

The invention discloses a layout graph filling method. The method comprises the steps of providing a design layout comprising an auxiliary active layer, a redundant active layer, an auxiliary gate layer and a redundant gate layer; selecting an auxiliary active layer of which the line width is within a first preset line width range and a redundant active layer of which the line width is within a second preset line width range; for the auxiliary active layer with the line width within a first preset line width range, adding an auxiliary silicon-germanium layer on the auxiliary active layer smaller than the first preset line width, and adding an auxiliary silicon-germanium layer on at least one auxiliary active layer larger than the first preset line width; and for the redundant active layerof which the line width is within a second preset line width range, determining the style of the redundant silicon-germanium layer to be added according to the graph around the redundant active layer,and adding the redundant silicon-germanium layer. The substrate patterns in the germanium-silicon pattern growth region are classified, and different filling modes are adopted according to the substrate patterns with different line widths, so that the defect problem caused by a pattern load effect is solved to a certain extent.

Description

technical field [0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a method for filling layout patterns in the manufacturing process of semiconductor devices. Background technique [0002] With the continuous shrinking of the technology node of semiconductor manufacturing, the process is becoming more and more complex. In order to make the silicon germanium (SiGe) pattern can be epitaxially grown on the substrate better, the effective density of the silicon germanium pattern needs to meet the requirements of the online process. Therefore, in Silicon germanium redundant patterns and device auxiliary patterns are introduced in the manufacturing process of semiconductor devices. [0003] However, the applicant found that in the actual manufacturing process of semiconductor devices, on a substrate pattern with a large growth area, due to the influence of the pattern growth load effect, silicon germanium cannot be effect...

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Problems solved by technology

[0003] However, the applicant found that in the actual manufacturing process of semiconductor devices, on a substrate pattern with a large growth area, due to the influence of the pattern growth load effect, silicon germanium cannot be effectively grown uniformly on the substrate surface, resulting in the final formation of Silicon germanium pattern will produce pit defects in the middle area

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