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Two-sided memory array

A storage array and array technology, applied in the storage field, can solve the problems of circuit area increase, etc., and achieve the effect of simple circuit, increased circuit occupation area, and easy implementation

Active Publication Date: 2020-02-21
WUHAN XINXIN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, adding additional transistors and corresponding signals can lead to an increase in circuit area. At the same time, the vertical size of the memory cell array is limited by about 2.47nm, which poses a challenge to the layout of the local X decoder.

Method used

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Experimental program
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Embodiment Construction

[0032] Figure 2A Shown is the local X decoder with extra transistors and signals, Figure 2B Shown is an array of Flash cells containing eight local X decoders, where each local X decoder is Figure 2A Native X decoder shown. Please refer to Figure 2A and Figure 2B , the core idea of ​​the present invention is that in order to solve Figure 1A The existing local X decoder as shown makes programmed cells become erased cells (that is, the corresponding memory cells are selected during the erase operation), which eventually leads to the problem that programmed data is easily lost. Figure 1A The local X decoder shown is based on the addition of transistors P1, P2 and N10. Due to the existence of transistors P1 and P2, it can ensure that the gate of P0 has a potential of 9V, so it is always in an off state, so as to ensure that the word line WL connected to it can always be in a floating state when it is in erase mode and not selected, and its The potential is the bottom po...

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Abstract

The invention discloses a two-sided memory array comprising a central Flash memory cell array, wherein four local X decoders are connected to each of two opposite sides of the flash memory cell array.Each of the local X decoders includes eight transistors. Compared with an existing local X decoder, the local X decoder is provided with only three additional transistors to avoid the problem of thememory cell being selected during ab erase operation. The circuit is simple and easy to implement, and eight local X decoders are distributed on the two opposite sides of the central flash memory cellarray so as to adapt to the pitch of eight word lines in the prior art and not significantly increase the circuit area.

Description

technical field [0001] The invention relates to storage technology, in particular to a double-sided storage array. Background technique [0002] The storage array may include multiple local X-decoders. Recent developments in the semiconductor field have increased the number of transistors in the local X-decoder, but at the same time it is necessary to consider how to make the output signal of the local X-decoder prevent the memory cell from being selected during the erase operation. [0003] refer to Figure 1A , which shows the existing native X decoder. The local X decoder includes PMOS transistor P0, NMOS transistor N1 and NMOS transistor N2. The gate of the PMOS transistor P0 is connected to the voltage signal GWLb, the source of the PMOS transistor P0 and the substrate N well are connected to the voltage signal PWL, the drain of the PMOS transistor P0 is connected to the drain of the NMOS transistor N1, and the gate of the NMOS transistor N1 is connected to the voltag...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/04G11C16/08H01L27/115H10B69/00
CPCG11C16/0483G11C16/08H10B69/00
Inventor 唐原徐仁泰
Owner WUHAN XINXIN SEMICON MFG CO LTD