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A method of testing pll stability of hdmi through soc

A technology of stability and reference clock, applied in the field of HDMI video, can solve the problem of high price and achieve the effect of low cost and simple operation

Active Publication Date: 2021-12-21
JINGCHEN SEMICON SHENZHEN CO LTD
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  • Application Information

AI Technical Summary

Problems solved by technology

[0002] Phase Locked Loop (PLL: Phase Locked Loop) plays a pivotal role in SOC (System On Chip), especially whether the PLL of HDMI (High Definition Multimedia Interface) is stable or not, determines whether the HDMI signal in SOC can be Normal output; the existing technology uses an oscilloscope to measure the jitter of the HDMI output signal. According to the jitter of the HDMI output signal, the PLL stability of the HDMI is obtained. The measurement by the oscilloscope also requires an active probe, the price of the oscilloscope and the active probe Expensive; therefore, there is an urgent need for a simple, low-cost HDMI PLL stability test method

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  • A method of testing pll stability of hdmi through soc

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Embodiment Construction

[0018] In order to describe the technical solution of the present invention more clearly and completely, the present invention will be further described below in conjunction with the accompanying drawings.

[0019] Please refer to figure 1 , the present invention proposes a method for testing the PLL stability of HDMI by SOC, and the SOC controls HDMI signal output, and the method for testing the PLL stability of HDMI by SOC includes the following steps:

[0020] S1: The nominal frequency value of the reference clock crystal for obtaining the SOC is A Hz;

[0021] S2: The actual frequency value of the reference clock crystal for measuring SOC is B Hz;

[0022] S3: Calculate the frequency offset of the reference clock crystal of the SOC by [(B-A) / A] to be C PPM;

[0023] S4: The actual frequency value of the HDMI signal output by the reference clock crystal for measuring SOC after passing through the PLL is D Hz;

[0024] S5: Obtain the output nominal frequency value of the ...

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Abstract

The present invention proposes a method for testing the PLL stability of HDMI through the SOC, and the SOC controls the HDMI signal output, including the following steps: S1: obtaining the nominal frequency value of the reference clock crystal of the SOC is A Hz; S2: measuring the reference clock of the SOC The actual frequency value of the crystal is B Hz; S3: Calculate the frequency offset of the SOC reference clock crystal by [(B‑A) / A] to be C PPM; S4: Measure the HDMI signal output by the SOC reference clock crystal after passing through the PLL The actual frequency value of is D Hz; S5: Obtain the nominal output frequency value of the HDMI signal set by the SOC is E Hz; S6: Calculate the frequency offset of the HDMI signal by [(D‑E) / E] to be F PPM; The PLL stability of HDMI can be judged according to the absolute value of the difference between F PPM and C PPM.

Description

technical field [0001] The invention relates to the field of HDMI video, in particular to a method for testing the PLL stability of HDMI through SOC. Background technique [0002] Phase Locked Loop (PLL: Phase Locked Loop) plays a pivotal role in SOC (System On Chip), especially whether the PLL of HDMI (High Definition Multimedia Interface) is stable or not, determines whether the HDMI signal in SOC can be Normal output; the existing technology uses an oscilloscope to measure the jitter of the HDMI output signal. According to the jitter of the HDMI output signal, the PLL stability of the HDMI is obtained. The measurement by the oscilloscope also requires an active probe, the price of the oscilloscope and the active probe Expensive; therefore, there is an urgent need for a simple and low-cost HDMI PLL stability testing method. Contents of the invention [0003] In order to solve the above problems, the present invention proposes a method for testing the stability of PLL of...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04N17/00G01R31/28
CPCH04N17/00G01R31/2843
Inventor 王政冯杰张坤
Owner JINGCHEN SEMICON SHENZHEN CO LTD
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