ADC sampling data recognition method and system, integrated circuit and decoding device

A technology of sampling data and identification method, applied in the direction of code conversion, electrical components, analog/digital conversion, etc., can solve the problem of unidentifiable starting position and synchronization state of sampling data, and achieve real-time synchronization, simplify synchronization and post-calibration steps, the effect of eliminating synchronization errors and data jitter

Active Publication Date: 2020-05-05
SUZHOU RIGOL PRECISION ELECTRIC TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to solve the problem that the start position and synchronization state of the sampling data between the time-interleaved ADCs in the high-speed data acquisition system cannot be identified in the time-alternating parallel sampling technology

Method used

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  • ADC sampling data recognition method and system, integrated circuit and decoding device
  • ADC sampling data recognition method and system, integrated circuit and decoding device
  • ADC sampling data recognition method and system, integrated circuit and decoding device

Examples

Experimental program
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other Embodiment approach

[0053] In other implementation manners, step 130 combines the serial data and the generated preamble sequence to obtain new serial data, including:

[0054] If the number of preambles in the preamble sequence has been limited when the preamble sequence is generated, the generated preamble sequence is added before the serial data or replaces the serial data to obtain new serial data, or each time a preamble is generated, The generated preambles are added before or replace the serial data until a predetermined number of preambles are generated.

[0055] This embodiment can reduce the power consumption of the preamble sequence generation device.

[0056] Step 140, generating a clock signal matching the new serial data, sending the clock signal to the decoding device, and the decoding device identifies the sampling data according to the new serial data and the clock signal. The splicing process changes the start and end positions of the data, which will lead to changes in the tim...

other Embodiment approach

[0058] In other embodiments, in order to support a common decoding device and facilitate decoding, the rising and falling edges of the clock signal are aligned with the data center of the new serial data.

[0059] Correspondingly, in one embodiment of the present invention, there is also provided a figure 1 The ADC sampling data identification method applicable to the decoding device used in conjunction, such as figure 2 shown, including:

[0060] Step 210, receiving the new serial data and clock signal sent by the ADC integrated circuit, wherein the new serial data is formed by combining the serial data and the preamble sequence, and the serial data is converted from the sampling data of n time-interleaved ADC chips Yes, the clock signal matches the new serial data.

[0061] Step 220, according to the agreement with the ADC integrated circuit, obtain the preamble sequence for splicing.

[0062] Step 230, according to the new serial data, the clock signal and the preamble ...

other Embodiment approach

[0082] In other embodiments, the combination module 430 combines the serial data and the generated preamble sequence to obtain new serial data, including: if the number of preambles in the preamble sequence has been limited when the preamble sequence is generated, then Add the generated preamble sequence to the serial data or replace the serial data to obtain new serial data, or each time a preamble is generated, add the generated preamble to the serial data or replace the serial data until a predetermined number of preambles.

[0083] The supporting clock generation module 440 is used to generate a clock signal matching the new serial data, and send the clock signal to the decoding device. In some embodiments, in order to support a general-purpose decoding device and facilitate decoding, the clock signal generated by the supporting clock generation module is a DDR clock signal (that is, the clock frequency is half of the data frequency), and the rising and falling edges of th...

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Abstract

The invention provides an ADC sampling data recognition method and system, an integrated circuit and a decoding device. The ADC sampling data recognition method comprises the following steps: identifying ADC sampling data; the ADC integrated circuit converts the sampling data of the n time-interleaved ADC chips into serial data, generates a lead code sequence, splits the serial data and the lead code sequence to obtain new serial data, sends the new serial data to the decoding device, generates a clock signal matched with the new serial data, and sends the clock signal to the decoding device;and the decoding device receives the new serial data and the clock signal sent by the ADC integrated circuit, obtains a lead code sequence for splicing according to the agreement with the ADC integrated circuit, and identifies the starting position of the sampling data of the time-interleaved ADC chip according to the new serial data, the clock signal and the lead code sequence for splicing. According to the invention, the starting position and the synchronization state of the sampling data can be judged under the condition of not changing the working mode of each time-interleaved ADC chip.

Description

technical field [0001] The invention relates to the field of high-speed data acquisition, in particular to an ADC sampling data identification method and system, an integrated circuit and a decoding device. Background technique [0002] With the advancement of technology and engineering applications, the sampling rate required by the data acquisition system is getting higher and higher. Under the limitation of the sampling rate of the existing single-core ADC, the time-alternating parallel sampling technology (time-interleaved ADC) is the best and effective technical way to realize a data acquisition system with a higher sampling rate. The application process of time-interleaved ADC involves technologies such as sampling aperture error calibration, signal gain error calibration and offset error calibration of multi-core ADC. Know exactly where the sampled data starts between the time-interleaved ADCs and the synchronization status of each ADC. [0003] In the prior art, th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/12
CPCH03M1/1285H03M1/1215H03M1/0624H04L7/04H03M1/121H03M1/1255
Inventor 严波方超敏王悦王铁军李维森
Owner SUZHOU RIGOL PRECISION ELECTRIC TECH
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