Chip packaging structure and manufacturing method thereof

A chip packaging structure and manufacturing method technology, applied in the direction of electrical components, electrical solid devices, circuits, etc., can solve the problems of limiting the number of chip I/O ports, low heat dissipation efficiency inside the multi-chip package, etc., and achieve a compact structure of the package , Solve the effect of insufficient heat dissipation efficiency and high-efficiency internal heat dissipation

Inactive Publication Date: 2020-05-08
SHANGHAI XIANFANG SEMICON CO LTD +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the defects in the prior art that the internal heat dissipation efficiency of the m

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  • Chip packaging structure and manufacturing method thereof
  • Chip packaging structure and manufacturing method thereof
  • Chip packaging structure and manufacturing method thereof

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Embodiment Construction

[0048] The technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0049] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "inner" and "outer" are based on the Orientation or positional relationship is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus s...

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Abstract

The invention provides a chip packaging structure and a manufacturing method thereof. The chip packaging structure comprises a substrate which is provided with a flow guide hole penetrating through the front surface and the back surface of the substrate; a first chip which is electrically connected with the substrate; a flow guide assembly which is arranged on the base plate, wherein a heat dissipation pipeline is arranged in the flow guide assembly, and the heat dissipation pipeline is communicated with the flow guide holes; a second chip which is arranged at one side, deviating from the first chip, of the flow guide assembly and is electrically connected with the substrate; and a plastic package body which packages the first chip, the flow guide assembly and the second chip. According tothe chip packaging structure provided by the invention, more efficient internal heat dissipation of the multi-chip packaging body is realized, and the problem of insufficient heat dissipation efficiency of a surface heat dissipation structure is effectively solved; circuit leading-out of the two chips is not interfered by the diversion assembly, and the number of I/O ports of the chips is not limited.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a chip packaging structure and a manufacturing method thereof. Background technique [0002] With the popularization of wireless electronic devices, the feature size of integrated circuits continues to shrink, and the interconnection density of devices continues to increase. Three-dimensional chip packaging has become a development trend, but this type of packaging will also introduce the problem of poor heat dissipation while improving the packaging integration. At present, the traditional heat dissipation structure and device design mainly focus on improving the heat dissipation on the surface of the package, and the improvement of heat dissipation inside the package is very limited. [0003] In order to solve the problem of heat dissipation inside the package, Chinese patent document CN105140205A discloses a double-sided heat dissipation semiconductor laminate...

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Application Information

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IPC IPC(8): H01L23/31H01L23/367H01L23/46H01L25/065
CPCH01L23/3121H01L23/367H01L23/46H01L25/0657H01L2225/06589H01L2224/73253H01L2224/73265H01L2224/92247H01L2924/181H01L2924/00012
Inventor 张凯曹立强
Owner SHANGHAI XIANFANG SEMICON CO LTD
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