Chip packaging structure and manufacturing method thereof

Abstract

The invention provides a chip packaging structure and a manufacturing method thereof. The chip packaging structure comprises a substrate which is provided with a flow guide hole penetrating through the front surface and the back surface of the substrate; a first chip which is electrically connected with the substrate; a flow guide assembly which is arranged on the base plate, wherein a heat dissipation pipeline is arranged in the flow guide assembly, and the heat dissipation pipeline is communicated with the flow guide holes; a second chip which is arranged at one side, deviating from the first chip, of the flow guide assembly and is electrically connected with the substrate; and a plastic package body which packages the first chip, the flow guide assembly and the second chip. According tothe chip packaging structure provided by the invention, more efficient internal heat dissipation of the multi-chip packaging body is realized, and the problem of insufficient heat dissipation efficiency of a surface heat dissipation structure is effectively solved; circuit leading-out of the two chips is not interfered by the diversion assembly, and the number of I / O ports of the chips is not limited.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a chip packaging structure and a manufacturing method thereof. Background technique [0002] With the popularization of wireless electronic devices, the feature size of integrated circuits continues to shrink, and the interconnection density of devices continues to increase. Three-dimensional chip packaging has become a development trend, but this type of packaging will also introduce the problem of poor heat dissipation while improving the packaging integration. At present, the traditional heat dissipation structure and device design mainly focus on improving the heat dissipation on the surface of the package, and the improvement of heat dissipation inside the package is very limited. [0003] In order to solve the problem of heat dissipation inside the package, Chinese patent document CN105140205A discloses a double-sided heat dissipation semiconductor laminate...

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Problems solved by technology

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the defects in the prior art that the internal heat dissipation efficiency of the multi-chip package is not high and the number of chip I / O ports is limited, thereby providing a chip package structure with a heat dissipation pipeline and its Production Method

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