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Bulk layer transfer processing with backside silicidation

A body and semiconductor technology, applied in the field of body layer transfer processing, can solve the problems of increasing cost, expensive SOI wafers and processing substrates, etc.

Pending Publication Date: 2020-05-08
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

While increasing the spacing between the switching device and the underlying substrate can greatly improve the RF performance of a CMOS switch, using HR silicon or sapphire to process the wafer can significantly increase the cost
That is, using SOI wafers and handling substrates is quite expensive relative to the cost of bulk semiconductor wafers

Method used

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  • Bulk layer transfer processing with backside silicidation
  • Bulk layer transfer processing with backside silicidation
  • Bulk layer transfer processing with backside silicidation

Examples

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Embodiment Construction

[0019] The detailed description set forth below, in conjunction with the accompanying figures, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details in order to provide a thorough understanding of various concepts. It will be apparent, however, to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring the concepts.

[0020] As used herein, the use of the term "and / or" is intended to mean an "inclusive or" and the use of the term "or" is intended to mean an "exclusive or". As described herein, the term "exemplary" is used throughout the specification to mean "serving as an example, instance or illustration" and should not necessarily be construed as preferred or a...

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Abstract

A radio frequency integrated circuit (RFIC) includes a bulk semiconductor die. The RFIC also includes a first active / passive device on a first-side of the bulk semiconductor die, and a first deep trench isolation region extending from the first-side to a second-side opposite the first-side of the bulk semiconductor die. The RFIC also includes a contact layer on the second-side of the bulk semiconductor die. The RFIC further includes a second-side dielectric layer on the contact layer. The first deep trench isolation region may extend through the contact layer and into the second-side dielectric layer.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of U.S. Patent Application No. 15 / 975,434, filed May 9, 2018, entitled "BULK LAYER TRANSFER PROCESSING WITH BACKSIDE SILICIDATION," which claims the title "BULK LAYER TRANSFER PROCESSING WITH BACKSIDE SILICIDATION," U.S. Provisional Patent Application No. 62 / 565,495, the disclosure of which is expressly incorporated herein by reference in its entirety. technical field [0003] The present disclosure generally relates to integrated circuits (ICs). More specifically, the present disclosure relates to bulk layer transfer processing utilizing backside silicidation. Background technique [0004] Designing mobile radio frequency (RF) chips (eg, mobile RF transceivers) is complicated by the addition of circuit functionality to support communication enhancements. Designing these mobile RF transceivers may involve the use of semiconductor-on-insulator technology. Semiconductor-on-insulato...

Claims

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Application Information

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IPC IPC(8): H01L21/762H01L23/48H01L23/522
CPCH01L23/522H01L21/76229H01L21/76898H01L23/481H01L28/10H01L28/40H01L21/823475H01L21/823481H01L25/0657H01L25/117
Inventor S·格科特佩里G·P·埃姆图尔恩S·A·法内利
Owner QUALCOMM INC
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