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Hardware SAT solver based on pipeline execution strategy

An execution strategy and pipeline technology, applied in the computer field, can solve a large number of problems such as clock overhead, delay, and low system throughput, and achieve the effect of increasing the working clock frequency and throughput, and enhancing processing capabilities

Inactive Publication Date: 2020-05-12
NAT UNIV OF DEFENSE TECH
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Problems solved by technology

Therefore, if the clause is empty, then the clause cannot be satisfied, so the simplified formula is also unsatisfiable
[0006] Most of the existing hardware SAT solvers are executed sequentially. When multiple steps are executed, it often takes multiple clock cycles to wait for the next step after the completion of the previous step. This creates a delay and brings a lot of problems. The clock overhead, the throughput of the system is low

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  • Hardware SAT solver based on pipeline execution strategy
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  • Hardware SAT solver based on pipeline execution strategy

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[0034]The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0035] In an optional embodiment, the present invention provides a structure of a hardware SAT solver based on a pipeline execution strategy, such as figure 1 As shown, it includes a preprocessing module 1 , a clause search and argument inversion module 5 and an output module 7 .

[0036] Among them, the preprocessing module 1 is used to generate the initial assignment of the CNF formula variable, extract the unsatisfiable clauses under the current assignment and the clause and variable information of the formula; the output module 7 is used to output the CNF formula Is it satisfiable.

[0037] Clause search and variable element flipping module 5, used to search for unsatisfiable clauses acco...

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Abstract

The invention provides a hardware SAT solver based on a pipeline execution strategy. The hardware SAT solver comprises a preprocessing module, an output module and a clause searching and variable element overturning module. The preprocessing module is used for generating an initial assignment of a CNF formula variable, and extracting unsatisfied clauses under the current assignment and clauses andvariable information of the CNF formula; the output module is used for outputting whether the CNF formula can be met or not; and the clause searching and variable element overturning module is used for synchronously and circularly executing the search of the unsatisfactory clauses by the first thread, the second thread, the third thread and the fourth thread according to a pipeline execution strategy within the preset maximum specified times, overturning clause variable elements according to a certain probability and storing the unsatisfactory clauses after the variable elements are overturned. According to the hardware SAT solver, a pipeline strategy is adopted in the SAT problem solving process, pipeline parallel solving is achieved, the working clock frequency and the throughput rate of a hardware system are increased, and the processing capacity of the solver is enhanced.

Description

technical field [0001] The invention belongs to the technical field of computers, and in particular relates to a SAT solver, in particular to a hardware SAT solver based on a pipeline execution strategy. Background technique [0002] In the SAT problem (satisifiability problem, Boolean satisfiability problem), given a set of finite variable set X={x 1 ,x 2 ,...,x n},x n Can be assigned true (1) or false (0), the literal l i is the variable x i or its negation and have Clause C is formed by text disjunction (meaning "or"), and the conjunction CNF (conjectured normal formula) formula Formed by the conjunction of several clauses, such as That is, a CNF formula consisting of 5 variables and 4 clauses. If any word in a clause is assigned a value of true, then the clause is true or satisfied; if all the words in a clause are assigned a value of false at the same time, it is said that the specified assignment makes the clause false, or the specified assignment makes ...

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Application Information

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IPC IPC(8): G06F9/38
CPCG06F9/38
Inventor 张建民马柯帆陆平静孙岩董德尊罗章欧洋王强齐星云曹继军戴艺
Owner NAT UNIV OF DEFENSE TECH
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