Logic synthesis result-oriented hierarchical structure optimization method, device and system

Abstract

The invention discloses a logic synthesis result-oriented hierarchical structure optimization method, device and system, comprising: a front-end logic synthesis device generates a synthesized netlist; a back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device And judge whether the hierarchical structure of the read synthesized netlist needs to be optimized; if so, generate a hierarchical structure optimization instruction and feed it back to the front-end logic synthesis device; when receiving the hierarchical structure optimization instruction, the front-end logic synthesis device will be based on the hierarchical structure. Optimize instructs to perform optimization operations on the hierarchy of the post-synthesis netlist to generate a new post-synthesis netlist. It can be seen that the implementation of the present invention can realize the optimization of the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization instruction fed back by the back-end processing device, thereby improving the quality of the front-end logic synthesis and the hierarchical structure in the synthesized netlist generated by the front-end logic synthesis. The matching degree of the actual requirements of the back-end is conducive to improving the design timing and reducing power consumption.

Description

technical field [0001] The present invention relates to the technical field of FPGA, and in particular, to a hierarchical structure optimization method, device and system guided by the result of logic synthesis. Background technique [0002] The design process of FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) is the process of developing FPGA chip using EDA (Electronics Design Automation, Electronic Design Automation) development software and programming tools. The development process of EDA development software mainly includes the front-end logic synthesis process and the back-end layout and routing, timing analysis and power consumption analysis. Convert it into a device netlist and optimize the device netlist. The back end places the device netlist generated by the front end on a specific position of the FPGA chip and performs routing according to the mapping relationship between the devices, and finally outputs the layout and routing results. The qu...

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Problems solved by technology

[0004] However, practice has found that when the synthesis tool needs to synthesize across modules, the newly generated device will change the hierarchical structure of the user design, and each stage of synthesis may involve the use and modification of the hierarchical structure of the user design, and it is difficult to ensure that each level The modification of the structure is consistent with the user's design itself. Every modification of the hierarchical structure of the user's design will affect the subsequent logic synthesis, layout and routing, etc., resulting in a mismatch between the hierarchical structure of the synthesized netlist and the requirements of the back-end algorithm. This will lead to problems such as unreasonable layout and routing results at the back end, difficulty in improving design timing, and difficulty in reducing power consumption.

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