Main control chip operation state control device and method

Abstract

The invention discloses a main control chip operation state control device and method. The method comprises the steps that a three-state gate is arranged between a PHY chip and a main control chip; the operation state of the main control chip is from startup to shutdown: firstly, the three-state gate is closed to enable the PHY chip to be in a high-level working state, and the power failure of themain control chip is executed, wherein the operation state of the main control chip is from shutdown to startup, the main control chip is powered on, the three-state gate is opened, and the main control chip resets the PHY chip. The device is used for performing a method. By arranging the three-state gate isolation PHY chip and the main control chip, the stability during operation state switchingcan be improved.

Description

technical field [0001] The invention relates to the field of industrial electronic control systems, in particular to a device and method for controlling the operating state of a main control chip. Background technique [0002] At present, existing industrial electronic products generally use a single-chip microcomputer to wake up the main control CPU system. The single-chip microcomputer executes the power on and off of the main control CPU system by obtaining the network signal. The disadvantage of this solution is: the single-chip microcomputer that supports the network can realize the remote power on and off. At this time, the single-chip microcomputer and the main control CPU need 2 IPs. A built-in switch is required to realize the function of wake-up on LAN, which increases the cost and power consumption of the system, and the cost performance is not high. [0003] An existing solution is to use a PHY chip to enable industrial electronic products to complete shutdown ...

AI Technical Summary

Problems solved by technology

The microcontroller is connected to execute the power on and off of the main control CPU system by obtaining the network signal. The disadvantage of this solution is: a single chip microcomputer that supports the network can be used to realize remote power on and off.

However, a key point in the control process is the reset control. Generally, the CPU needs to reset the PHY after power-on, because the PHY is always powered. After the main control CPU is powered off, it comes through the GMII / RGMII / MII / RMII interface. The signal of the CPU will cause the port of the CPU to be powered, which will cause the PHY reset signal to be abnormal, so that the wake-up function cannot be realized

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