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Server mainboard testing method

A test method and server technology, applied in fault hardware test methods, instruments, error detection/correction, etc., can solve problems such as low efficiency, trouble for R&D personnel, waste of time and manpower, etc.

Active Publication Date: 2020-05-22
MITAC COMP (SHUN DE) LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, generally speaking, the number of servers to be tested is huge and peripheral devices need to be connected each time, which is not only a waste of time and manpower, but if the number of peripheral devices is insufficient for the number of servers, it will be necessary to perform server tests in batches or wait for idle peripherals The test can only be carried out when the device is installed, causing confusion and inconvenience to the R&D personnel
And in the R&D and production process, when the verification server executes the reset (Reset) test, most of the problems and abnormalities occurred during the verification server's execution of the Basic Input Output System (BIOS) POST (Power on Self Test), but each time All need to enter the OS to complete the verification, which is a waste of time and inefficient, and needs to be explored and improved.

Method used

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Embodiment Construction

[0013] refer to figure 1 and figure 2 , the server motherboard testing method of the present invention is applied on a server motherboard 1, and the server motherboard 1 includes a processing unit 2, a platform path controller 3 connected to the processing unit 2, and a basic platform path controller 3 connected to the platform path controller 3. Input output unit 4. The basic input and output unit 4 includes an execution module 41 and a test module 42 . The test module 42 has a test function parameter, a first power-on test mode, and a second power-on test mode. The server main board testing method includes a step (A), a step (B), a step (C), a step (D) and a step (E).

[0014] First, in the step (A), the server motherboard 1 is turned on, and the processing unit 2 receives and executes the basic input and output unit 4 (BIOS, Basic Input / Output System) execution module 41. In this step (B), when the processing unit 2 executes the execution module 41 of the basic input...

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Abstract

The invention discloses a server mainboard testing method, which is applied to a server mainboard. The server mainboard comprises a processing unit, a platform path controller and a basic input / outputunit. The basic input / output unit comprises an execution module and a test module. The server mainboard testing method comprises the following steps: in a step (B), when the processing unit executesthe execution module and reads an execution parameter built in the execution module, the processing unit determines if the read execution parameter is a first bit value or not, and if not, the processing unit continues to execute the execution module and completes startup; and step C, if the read execution parameter is determined to be a first bit value in step B, the processing unit directly executes the test module. Therefore, when the processing unit judges that the execution parameter is the first bit value, the processing unit directly executes the test module to perform the test operation, so that the inconvenience that the server mainboard needs to be externally connected with a peripheral device with an operation system in the past is effectively improved, the time is saved, and the test efficiency is good.

Description

technical field [0001] The invention relates to a testing method for a server mainboard, in particular to a time-saving and efficient testing method for a server mainboard. Background technique [0002] Servers are widely used nowadays, and server motherboards need to undergo various tests before leaving the factory to ensure their functionality and stability. Therefore, it is common to have items that need to be tested and verified in each stage of the server motherboard manufacturing process, so as to find problems in time and make abnormal improvements, so as to ensure the execution of subsequent work sites. Generally speaking, during the R&D stage, it is common to execute the reset (Reset) test operation of the Basic Input / Output System (BIOS, Basic Input / Output System), such as: warm reset (Warm reset / Soft reset) or full reset (Full reset) reset / Powercycle reset) operations, etc., but to perform these reset (Reset) operations for testing, it is often necessary to conne...

Claims

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Application Information

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IPC IPC(8): G06F11/22
CPCG06F11/2205G06F11/2273Y02D10/00
Inventor 王启禹曹登云
Owner MITAC COMP (SHUN DE) LTD
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