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Decoding method and device and decoder

A decoding device and decoder technology, which are applied in the directions of coding, code conversion, coding components, etc., can solve the problems of high parallelism and hardware resource consumption of the decoder, difficult to apply flexibly, etc., and achieve the effect of improving application flexibility.

Pending Publication Date: 2020-06-02
ZTE CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] Embodiments of the present invention provide a decoding method, device, and decoder to at least solve the problems of high hardware resource consumption and difficulty in flexible application caused by excessive parallelism of decoders in the related art

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  • Decoding method and device and decoder
  • Decoding method and device and decoder
  • Decoding method and device and decoder

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Embodiment 1

[0043] The decoding implementation process of the present invention will be described in detail below in conjunction with Embodiment 1. To facilitate the description of the scheme, first define the meanings of the relevant symbols as follows:

[0044] P: hardware parallelism of the designed decoder;

[0045] Z set : The expansion factor set supported by the designed decoder;

[0046] Z: The expansion factor actually used by the code block to be decoded, Z∈Z set ;

[0047] T: the decoding time-sharing number of the code block to be decoded, that is, the time-sharing number;

[0048] t: Decoding time-sharing index number of the code block to be decoded, 0≤t≤T-1;

[0049] L: the number of basic matrix rows or layers used by the code block to be decoded;

[0050] l: the decoding layer index of the code block to be decoded, 0≤l≤L-1;

[0051] K: the number of basic matrix columns used by the code block to be decoded;

[0052] k: decoding column index of the code block to be ...

Embodiment 2

[0109] Embodiment 2 provides a decoder that implements the above decoding process, image 3 It is a structural block diagram of the decoder of this embodiment. Such as image 3 As shown, the decoder includes: an information splitting module 10 , a decoding module 20 and an information reassembly module 30 . The information splitting module 10 completes the soft information splitting function before decoding. The decoding module 20 completes the iterative calculation function of "hierarchical-time-division decoding". The information reorganization module 30 completes the reorganization output of the decoded hard bit information. Wherein, the information splitting module and the information recombining module can be located inside or outside the decoding device.

[0110] A specific implementation of the information splitting module 10 is as Figure 4 As shown, the module first calculates the available decoding time-sharing number T according to the preset decoder parallelis...

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Abstract

The invention provides a decoding method and device and a decoder, and the method comprises the steps: setting the parallelism degree P of the decoder, and carrying out the information splitting of the soft information of a to-be-decoded block according to the parallelism degree P; decoding calculation is carried out on the to-be-decoded block according to the splitting information, and outputtingdecoded hard bit information; carrying out information recombination on the hard bit information according to the parallelism degree P. According to the method disclosed inthe invention, the parallelism degree of the decoder can be flexibly selected according to the decoder throughput, the acceptable resource consumption, the hardware cost and the like required by the design during decoding design; thus the problems of high hardware resource consumption and difficulty in flexible application caused by overlarge parallelism degree can be solved, and the application flexibility of the decoder is improved.

Description

technical field [0001] The present invention relates to the field of decoding in wireless communication, in particular to a decoding method, device and decoder. Background technique [0002] With the continuous development of multimedia broadcasting, wireless communication, and VLSI (Very Large Scale Integration, VLSI) technology, Low Density Parity Check code (Low Density Parity Check, LDPC), as the forward error correction code closest to the Shannon limit, has been It is widely used in communication standards such as Digital Video Broadcast (DVB), Wireless Local Area Network (WLAN), Worldwide Interoperability for Microwave Access (WiMAX), and was selected for the first time as a 5G A data channel coding scheme for enhanced Mobile Broadband (eMBB) in a mobile communication system. Faced with the large-capacity, low-latency, and high-reliability business requirements in the future 5G (Generation) mobile communication system, as well as the requirements of various applicati...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11
CPCH03M13/1114H03M13/1111H03M13/114H03M13/116H03M13/6561H03M13/1108H03M13/1137
Inventor 张鹤唐雄章伟陈朝正李晓亮文奏章
Owner ZTE CORP
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