Arbitrary depth asynchronous FIFO memory

Abstract

An arbitrary depth asynchronous FIFO memory is provided. The asynchronous FIFO memory provided by the invention comprises a dual-port memory, a write address decoder, a read address decoder, a full detection unit, a read pointer synchronization unit, an empty detection unit and a write pointer synchronization unit, the write pointer decoder, the full detection unit and the read pointer synchronization unit are located in a first clock domain; the read pointer decoder, the null check unit and the write pointer synchronization unit are located in a second clock domain; the write pointer decodercoupled to a write port of the dual-port memory and providing a write pointer to the write port of the dual-port memory; the read pointer decoder is coupled to a read port of the dual-port memory andprovides a read pointer to the write port of the dual-port memory.

Description

technical field [0001] The present application relates to a storage circuit, in particular, to an asynchronous FIFO (First In First Out) memory of arbitrary depth. Background technique [0002] In the SOC (System OnChip, System on Chip) design of a multi-clock domain system, an asynchronous FIFO is often used to solve the problem of data transmission between different clock domains. After years of development, the design of asynchronous FIFO has become relatively mature, which can not only relax the timing requirements for data transmission in different clock domains, but also improve the transmission efficiency between them. [0003] figure 1 A block diagram showing a prior art asynchronous FIFO. [0004] see figure 1 , asynchronous FIFO includes 3 main parts, FIFO memory (dual port memory ( figure 1 DualPortRAM)), write unit and read unit. figure 1 The left part of the center is a writing unit for writing data to the FIFO memory, and the right part is a reading unit f...

AI Technical Summary

Problems solved by technology

[0009] In the pointer synchronization process, if the binary counter is directly used, the pointer synchronization error will be caused because the multi-bit data is flipped at the same time during the value jump process.

For example, when the pointer changes from 0b0111 to 0b1000, each bit of the data bit is reversed. If it is directly sampled by the asynchronous clock of the receiver at this time, any intermediate value may appear (the receiver may see to 0b0111→0b0101→0b1000), which may cause "full" / "empty" judgment error and cause misreading or miswriting of FIFO memory

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