Unlock instant, AI-driven research and patent intelligence for your innovation.

A method for embedding chips in cavities on the front and back sides of an adapter board

An adapter board and chip technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems of complex process and high cost, and achieve the effect of large economic benefits, large cost advantages, and broad application prospects

Active Publication Date: 2022-05-27
ZHEJIANG UNIV
View PDF20 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, for the adapter board with double-layer chip structure, it is generally necessary to make a double-layer adapter board, then embed different chips into each layer of the adapter board, and then perform wafer-level bonding on the adapter board. The process is complicated and higher cost

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A method for embedding chips in cavities on the front and back sides of an adapter board
  • A method for embedding chips in cavities on the front and back sides of an adapter board
  • A method for embedding chips in cavities on the front and back sides of an adapter board

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0057] Include:

[0058]A: Make TSV (silicon through hole) on a silicon wafer with a double layer SOI (Silicon-On-Insulator) layer, TSV stops on the surface of the second layer OFI, and electroplated metal fills TSV;

[0059] as Figure 1 As shown, the SOI wafer 101 is selected, wherein 102 is the SOI layer, the present silicon wafer has two layers of SOI, from top to bottom, the first layer of SOI layer 102 and the second layer of SOI layer;

[0060] as Figure 2 As shown, by lithography, etching process in the SOI silicon wafer surface to make TSV hole 103, hole diameter range from 1um to 1000um, depth in 10um to 1000um;

[0061] Etching stops on the second SOI layer;

[0062] as Figure 3 As shown, the insulation layer such as silicon oxide or silicon nitride is deposited above the silicon wafer, or direct thermal oxidation, and the thickness of the insulation layer ranges from 10nm to 100um; through physical sputtering, magnetron sputtering or evaporation process to make a seed l...

Embodiment 2

[0074] Include:

[0075] A: Make TSV on a silicon wafer with a double layer OFI layer, TSV stops at the surface of the second layer of SOI, continues to etch TSV to the lower surface of SOI, and electroplates the metal filled TSV;

[0076] as Figure 11As shown, select SOI silicon wafer, this silicon wafer has two layers of SOI; through lithography, etching process in the SOI silicon wafer surface to make TSV holes, hole diameter range from 1um to 1000um, depth in 10um to 1000um;

[0077] Etch TSV stops at the surface of the second layer of SOI and continues to etch TSV to the lower surface of SOI;

[0078] Deposition of silicon oxide or silicon nitride and other insulating layers above the silicon wafer, or direct thermal oxidation, the thickness of the insulation layer ranges from 10nm to 100um; through physical sputtering, magnetron sputtering or evaporation process to make a seed layer above the insulation layer, the thickness of the seed layer ranges from 1nm to 100um, which c...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
Login to View More

Abstract

The invention discloses a method for embedding chips in cavities on the front and back sides of an adapter board. In the second SOI layer, a silicon wafer with through-silicon holes is obtained, and then electroplated with metal to fill the through-silicon holes to obtain a metal-filled silicon wafer; then a groove is etched on the opening surface of the through-silicon hole, and the metal in the groove is etched Cavities are formed on both sides of the front and back sides to obtain an interposer board with grooves on both sides; a chip with solder is embedded, and then an RDL interconnection layer is made on the surface, and the second SOI layer is continued to be etched to fill the TSV One end of the metal pillar is exposed, the chip with solder balls is embedded, the filling gel is cured, and the surface gel is removed. The present invention realizes the purpose of embedding chips in both front and back sides of an adapter board by making an adapter board, making grooves on both sides, and then embedding chips into the grooves.

Description

Technical field [0001] The present invention relates to the field of chip packaging technology, specifically to a method of embedding a chip in the front and back cavities of the adapter board. Background [0002] Millimeter wave RF technology is developing rapidly in the semiconductor industry, and it is widely used in high-speed data communications, automotive radar, airborne missile tracking systems, and space spectral detection and imaging, and the market is expected to reach $1.1 billion in 2018, becoming an emerging industry. New applications put forward new requirements for the electrical performance, compact structure and system reliability of the product, for wireless transmission and reception systems, it is not yet possible to integrate into the same chip (SOC), therefore, the need to integrate different chips including RF units, filters, power amplifiers, etc. into a separate system to achieve the function of transmitting and receiving signals. [0003] The traditiona...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L21/50H01L21/56H01L21/60
CPCH01L21/76898H01L21/50H01L21/56H01L24/80
Inventor 郁发新冯光建王志宇张兵
Owner ZHEJIANG UNIV