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Processor capable of high effective actuating asynchronous event mission in multiple asynchronous missions

A technology for executing tasks and processors. It is applied in the direction of concurrent instruction execution, machine execution devices, and electrical digital data processing. It can solve problems such as increased power consumption, unsuitable for household equipment, and inability to determine the operating clock at a higher level. efficiency effect

Inactive Publication Date: 2003-07-02
GK BRIDGE 1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Doing so does not allow higher certainty of the operating clock
And if it is easy to make the operation clock high, t

Method used

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  • Processor capable of high effective actuating asynchronous event mission in multiple asynchronous missions
  • Processor capable of high effective actuating asynchronous event mission in multiple asynchronous missions
  • Processor capable of high effective actuating asynchronous event mission in multiple asynchronous missions

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0267] instruction

[0268] Determine whether the establishment of event i is true or false, such as event i

[0269] If it is established as false, the read destination address will not be entered in advance.

[0270] The mnemonic for this instruction is shown in (Example 2).

example 2

[0272] cmp_and_Wait cr_statei, immediate value

[0273] In (Example 2), cr_statei (i=0, 1, 2, 3...7) is described in the first operand, which means that any one of the seven state monitoring registers in the I / O processor can be indicated.

[0274] By combining the status monitoring register specified in the first operand with the immediate value specified in the second operand, it is possible to confirm whether any one of the 35 events is true. The above instruction is referred to as the Cmp_And_Wait instruction in the following description. Needless to say, it goes without saying that the above-mentioned event waiting loop judges whether the specified event is established or not for n times and negated according to the first operand and the second operand of the Cmp_And_Wait instruction.

[0275] Fig. 14A shows the configuration of a modified command readout circuit 10 in the third embodiment. IF1+1 storage unit 20, incremental circuit 21, IF2 storage unit 22, DECPC storag...

no. 4 example

[0305] The fourth embodiment relates to the technique of allocating more time slots to graphics output tasks during the horizontal blanking period and vertical blanking period of the display.

[0306] The I / O processor for increasing the time slot is realized by adding changes shown in FIGS. 2D to 21 to the configuration of the task management unit 15 in the first embodiment.

[0307] The I / O processor in the fourth embodiment is provided with an instruction memory 100, an instruction readout circuit 10, an instruction decoding control unit 81, an operation execution unit 84, and a task management unit 15, which has no difference from the third embodiment . The novelty of the fourth embodiment is that the task management register 13 monitors the emergency transition permission signal iexecmode.

[0308] Fig. 20 shows the internal structure of the task management unit 15 in the fourth embodiment.

[0309] The 3 bits in the task management register 13 in FIG. 20 use the 3 bits...

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Abstract

The counter 52 is set with an initial value of "1" and is a counter with a maximum value of "4". This counter 52 increments the count value held by the flip-flop 51 in synchronization with a clock signal so that the count value changes as shown by the progression 1,2,3,4,1, 2,3,4. This clock signal is also used by the instruction decode control unit 11 to control the execution of instructions, with the counting by the counter 52 being performed once for each instruction execution performed by the instruction decode control unit 11. The comparator 54 compares the count value counted by the counter 52 with the maximum value "4", and when the values match, sets the task switching signal chg_task_ex at a "High" value, so that the processing switches to the execution of the next task.

Description

technical field [0001] The present invention relates to a processor provided in an AV decoder for reproducing variable-code-length multimedia data beginning with an MPEG data stream, and responsible for peripheral control of a main processor inside a dedicated AV decoder. Background technique [0002] As another basic technology of the multimedia society, the reproduction technology of the MPEG data stream has seen an astonishing rise in demand in recent years. The reason why the reproduction technology of the MPEG data stream has attracted attention as a new active stage is that it is possible to perform interactive animation reproduction and sound reproduction in the field of civil equipment. Advanced research and development of AV decoders for MPEG stream reproduction. [0003] Although the processing to be performed in the reproduction technology of the MPEG stream is various, it is generally considered that they are roughly divided into core processing and asynchronous...

Claims

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Application Information

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IPC IPC(8): G06F9/30G06F9/38G06F9/48H04N7/26H04N7/50
CPCH04N19/00781H04N7/26702G06F9/4881G06F9/3851G06F9/3009H04N19/00478G06F9/30087H04N19/42H04N19/61G06F15/16
Inventor 田中卓敏前信洁平井诚吉冈康介清原督三
Owner GK BRIDGE 1