Via Post-Sensing Layer Distributor for Minimizing Latency and Overflow in Advanced Process

Abstract

The present invention relates to a via post sensing layer allocator that minimizes time delay and overflow under an advanced manufacturing process. The via post sensing layer allocator designs a layer allocation scheme according to the following steps: S1) Generate an initial solution for the subsequent stage; Apply the multi-angle congestion relaxation strategy to evaluate the congestion and then adjust the layer allocation scheme; S2) Based on the initial solution, apply the idea of ​​negotiation to guide the layer allocation; S3) Use the network healing algorithm to optimize the maximum delay of the current layer allocation scheme; S4) Sort all the nets according to the delay and redistribute them; give priority to the nets with large delays, that is, sequence-critical nets, and use the via post optimization method for the top timing-critical nets, combining via posts and non-default Rule lines to further reduce latency and generate the final layer assignment scheme. The via post-aware layer allocator can optimize delay and overflow under the premise of considering via congestion, wire congestion and coupling effects.

Description

technical field [0001] The invention belongs to the technical field of computer-aided design of integrated circuits, and in particular relates to a through-hole column sensing layer distributor which minimizes time delay and overflow under an advanced manufacturing process. Background technique [0002] As one of the important factors affecting chip performance, interconnection delay is an important optimization target in layer assignment. The line delay mainly includes the line delay and the via delay. However, with the expansion of the circuit scale, the wire resistance and the via resistance increase significantly, which directly leads to the increase of the wire network delay. In advanced processes, the upper layer has a larger line width and line spacing than the lower layer, so the resistance of the upper layer lines is lower. Therefore, allocating timing-critical network segments to the upper layer is beneficial to reduce delay. But this method alone is not enough ...

AI Technical Summary

Problems solved by technology

[0005] In addition, each routing layer has an upper limit on routing resources

Routability will deteriorate and line density will increase if too many lines are allocated to upper layers, or if via posts, non-default ruled lines are used excessively

Due to coupling effects, an increase in line density will lead to an increase in coupling capacitance, which in turn will cause an increase in time delay, which has a negative impact on the timing characteristics of the circuit

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