Heterogeneous multi-core processor for bus equipment connection adjustment

Abstract

The invention discloses a heterogeneous multi-core processor for bus equipment connection adjustment. The heterogeneous multi-core processor includes: an architecture bus, a bus equipment connected with the architecture bus, a first communication bus connected with the architecture bus, a first CPU and a sharing memory located in a preset range of the first communication bus and connected with thefirst communication bus; the first CPU is a CPU responsible for instant processing. According to the technical scheme, a first CPU (namely a CPU responsible for instant processing) and the sharing memory are both arranged in a preset range of a first communication bus; and the first CPU and the sharing memory are connected with the first communication bus, so that the instantaneity and isochronism of accessing the shared memory by the CPU responsible for instant processing can be better guaranteed, and the access efficiency of the shared memory by the CPU responsible for instant processing isimproved.

Description

technical field [0001] The present application relates to the technical field of multi-core processors, and more specifically, relates to a heterogeneous multi-core processor for bus device connection adjustment. Background technique [0002] In a heterogeneous multi-core processor, for the sake of chip resource allocation efficiency, codes on each core can share chip resources, such as architecture bus and shared memory, during runtime. [0003] At present, in heterogeneous multi-core processors, the CPU responsible for real-time processing and the shared memory are all hung on the architecture bus, so that the CPU can access the shared memory through the architecture bus. There are many bus devices such as bus masters and bus slaves, and the frequency of interaction between the architecture bus and the bus devices is different at different times, which will affect the time for the CPU to access the shared memory each time. Specifically, it will be in When the interaction ...

AI Technical Summary

Problems solved by technology

[0003] At present, in heterogeneous multi-core processors, the CPU responsible for real-time processing and the shared memory are all hung on the architecture bus, so that the CPU can access the shared memory through the architecture bus. There are many bus devices such as bus masters and bus slaves, and the frequency of interaction between the architecture bus and the bus devices is different at different times, which will affect the time for the CPU to access the shared memory each time. Specifically, it will be in When the interaction frequency is relatively small, the access time to the shared memory is accelerated and the access time is shortened. However, when the interaction frequency is relatively high, the CPU's access to the shared memory cannot be processed by the architecture bus in a timely manner. The access time is relatively long, that is to say, the immediacy and isochronism of the CPU's access to the shared memory cannot be better guaranteed, which will reduce the CPU's access performance to the shared memory

[0004] Take the architecture of i.MX 7DUAL and the architecture of ST STM32MP153A as examples, the details can be figure 1 and figure 2 ,in, figure 1 A schematic diagram showing the i.MX 7DUAL architecture in the prior art, figure 2 It shows a schematic diagram of the ST STM32MP153A architecture in the prior art. For the architecture of i.MX 7DUAL, because the shared memory is located on the AXI / AHB bus switching structure, Cortex-A7 and Cortex-M4 are also devices on this bus switching structure , from the Cortex-A7 and Cortex-M4 to access the shared memory, the path is the same, because the bus switching device is also connected to other bus devices, therefore, the shared memory between the Cortex-A7 and Cortex-M4 will be Access has an impact. For the ST STM32MP153A architecture, the shared memory SYSRAM is located on the AXI bus interconnection close to the Cortex-A7, which is far away from the Cortex-M4. The interaction between the bus and other bus devices causes the Cortex-A7 to have poor immediacy and isochronism in accessing the shared memory SYSRAM

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