Substrates for semiconductor packages
A technology for semiconductors and semiconductor tubes, applied in the field of substrates of semiconductor packages, can solve problems such as inability to detect short circuits
Pending Publication Date: 2020-07-21
INFINEON TECH AG
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- Summary
- Abstract
- Description
- Claims
- Application Information
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Problems solved by technology
Because the traces are electrically connected to each other, undesired shorts within the semiconductor package on the substrate tape may not be detected during tape testing (e.g., due to design or manufacturing defects)
Method used
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[0011] In the following specific embodiments, reference is made to the drawings constituting a part thereof, and specific embodiments in which the present disclosure can be practiced are shown by way of illustration in the drawings. In this regard, referring to the orientation of the described drawings, directional terms such as "top", "bottom", "front", "back", "leading", "trailing" and the like are used. Because the components of an embodiment can be positioned in many different orientations, the directional terminology is used for illustrative purposes and is by no means restrictive. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following specific embodiments should not be construed as restrictive, and the scope of the present disclosure is defined by the appended claims.
[0012] It should be understood that, unless specifically indicated ...
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The invention relates to substrates for semiconductor packages. A substrate includes a dielectric layer, a first metal bar, a plurality of first traces, a plurality of first openings, a second metal bar, and at least one second opening. The dielectric layer has a first major surface and a second major surface opposite to the first major surface. The first metal bar is on the first major surface. The plurality of first traces are on the first major surface. Each first trace is connected at one end to the first metal bar. The plurality of first openings expose the dielectric layer on the first major surface and intersect a first trace. The second metal bar is on the second major surface. The at least one second opening exposes the dielectric layer on the second major surface and intersects the second metal bar. The first openings are laterally offset with respect to the at least one second opening.
Description
Background technique [0001] The substrate for semiconductor packages may be formed in a strip shape, and include traces on one or both main surfaces of the substrate strip to electrically connect to a plurality of semiconductor dies, which are then cut to provide a plurality of semiconductor packages. During the manufacturing process of the substrate tape, the traces on the main surface of the substrate tape may be electrically connected to each other to enable a plating process to plate portions of the traces. The semiconductor die can then be attached to the substrate tape and packaged with a molding material to provide a semiconductor package. Because the traces are electrically connected to each other, it may not be possible to detect undesired short circuits within the semiconductor package on the substrate tape during tape testing (for example, due to design or manufacturing defects). [0002] For these and other reasons, the present invention is needed. Summary of the inv...
Claims
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Login to View More IPC IPC(8): H01L23/498H01L21/48
CPCH01L23/49838H01L21/4846H01L2224/73265H01L2924/181H01L2224/48095H01L2224/73204H01L2924/15311H01L2224/48471H01L2224/48228H01L2924/15159H01L2924/18301H01L2224/32013H01L23/49816H01L23/49822H01L22/30H01L23/3128H01L2224/48227H01L2224/2919H01L2224/85455H01L2224/85444H01L24/32H01L24/29H01L2224/16227H01L2224/32225H01L24/13H01L24/16H01L24/48H01L2224/92247H01L24/73H05K1/0268H05K3/0097H05K3/242H01L2224/131H01L2224/291H01L2224/45099H01L2924/00012H01L2924/00H01L2224/16225H01L2924/00014H01L2924/014H01L23/3114H01L24/12H01L21/6835H01L24/97H01L21/4832H01L21/561
Inventor C·马尔贝拉曾庆麟
Owner INFINEON TECH AG